#Map Resource Utilization Report file generated by Lattice Radiant Software (64-bit) 2025.1.1.308.0 #Generated on 04/02/26 14:39:32 #DESIGN = lpddr4_axi_201 #DEVICE = LFCPNX-100 #PACKAGE = BBG484 #OPERATINGCONDITION = Commercial #PERFORMANCEGRADE = 9_High-Performance_1.0V
| LUT4 Logic |
LUT4 Distributed RAM |
LUT4 Ripple Logic |
PFU Registers | IO Buffers | EBR | |
|---|---|---|---|---|---|---|
| eval_top | 15479(33) | 1080(0) | 2356(0) | 10708(11) | 58(19) | 41(0) |
| ASYNC_AXI.u_aclk_pclk | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| lscc_pll_inst | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| kitcar_inst | 41(41) | 0(0) | 46(46) | 32(32) | 0(0) | 0(0) |
| kitcar_inst2 | 34(34) | 0(0) | 56(56) | 32(32) | 0(0) | 0(0) |
| osc_int_inst | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| lscc_osc_inst | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| u_mem | 11684(0) | 852(0) | 1690(0) | 7818(0) | 29(0) | 25(0) |
| lscc_lpddr4_mc_inst | 11684(1) | 852(0) | 1690(0) | 7818(187) | 29(0) | 25(0) |
| AXI_BI.u_axi_if | 921(0) | 420(0) | 372(0) | 1477(0) | 0(0) | 4(0) |
| u_rd | 426(65) | 114(0) | 342(10) | 797(107) | 0(0) | 4(0) |
| ASYNC.u_ctrl_fifo | 29(0) | 78(0) | 0(0) | 74(0) | 0(0) | 0(0) |
| u_fifo_dc | 29(29) | 78(78) | 0(0) | 74(74) | 0(0) | 0(0) |
| u_reorder_buff | 332(332) | 36(0) | 332(332) | 616(541) | 0(0) | 4(0) |
| EBR_CTRL[0].ASYNC.u_enable_bus_sync | 0(0) | 0(0) | 0(0) | 5(5) | 0(0) | 0(0) |
| EBR_CTRL[0].ASYNC.u_not_empty_sync | 0(0) | 0(0) | 0(0) | 2(2) | 0(0) | 0(0) |
| EBR_CTRL[1].ASYNC.u_enable_bus_sync | 0(0) | 0(0) | 0(0) | 5(5) | 0(0) | 0(0) |
| EBR_CTRL[1].ASYNC.u_not_empty_sync | 0(0) | 0(0) | 0(0) | 2(2) | 0(0) | 0(0) |
| EBR_CTRL[2].ASYNC.u_enable_bus_sync | 0(0) | 0(0) | 0(0) | 5(5) | 0(0) | 0(0) |
| EBR_CTRL[2].ASYNC.u_not_empty_sync | 0(0) | 0(0) | 0(0) | 2(2) | 0(0) | 0(0) |
| EBR_CTRL[3].ASYNC.u_enable_bus_sync | 0(0) | 0(0) | 0(0) | 5(5) | 0(0) | 0(0) |
| EBR_CTRL[3].ASYNC.u_not_empty_sync | 0(0) | 0(0) | 0(0) | 2(2) | 0(0) | 0(0) |
| EBR_CTRL[4].ASYNC.u_enable_bus_sync | 0(0) | 0(0) | 0(0) | 5(5) | 0(0) | 0(0) |
| EBR_CTRL[4].ASYNC.u_not_empty_sync | 0(0) | 0(0) | 0(0) | 2(2) | 0(0) | 0(0) |
| EBR_CTRL[5].ASYNC.u_enable_bus_sync | 0(0) | 0(0) | 0(0) | 5(5) | 0(0) | 0(0) |
| EBR_CTRL[5].ASYNC.u_not_empty_sync | 0(0) | 0(0) | 0(0) | 2(2) | 0(0) | 0(0) |
| EBR_CTRL[6].ASYNC.u_enable_bus_sync | 0(0) | 0(0) | 0(0) | 5(5) | 0(0) | 0(0) |
| EBR_CTRL[6].ASYNC.u_not_empty_sync | 0(0) | 0(0) | 0(0) | 2(2) | 0(0) | 0(0) |
| EBR_CTRL[7].ASYNC.u_enable_bus_sync | 0(0) | 0(0) | 0(0) | 5(5) | 0(0) | 0(0) |
| EBR_CTRL[7].ASYNC.u_not_empty_sync | 0(0) | 0(0) | 0(0) | 2(2) | 0(0) | 0(0) |
| u_ctrl_dpram | 0(0) | 36(0) | 0(0) | 19(0) | 0(0) | 0(0) |
| lscc_distributed_dpram_inst | 0(0) | 36(36) | 0(0) | 19(19) | 0(0) | 0(0) |
| u_lpddr4_mc_rd_rtrn_ebr_inst | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 4(0) |
| lscc_ram_dp_inst | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 4(0) |
| mem_main | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 4(0) |
| NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[0].no_init.u_mem0 | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[1].no_init.u_mem0 | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[2].no_init.u_mem0 | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[3].no_init.u_mem0 | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| u_wr | 495(326) | 306(0) | 30(30) | 680(343) | 0(0) | 0(0) |
| ASYNC.u_ctrl_fifo | 40(0) | 72(0) | 0(0) | 68(0) | 0(0) | 0(0) |
| u_fifo_dc | 40(40) | 72(72) | 0(0) | 68(68) | 0(0) | 0(0) |
| ASYNC.u_data_fifo | 74(0) | 222(0) | 0(0) | 188(0) | 0(0) | 0(0) |
| u_fifo_dc | 74(74) | 222(222) | 0(0) | 188(188) | 0(0) | 0(0) |
| u_int_fifo | 27(0) | 12(0) | 0(0) | 48(0) | 0(0) | 0(0) |
| u_fifo | 27(27) | 12(12) | 0(0) | 48(48) | 0(0) | 0(0) |
| u_rsp_fifo | 28(0) | 0(0) | 0(0) | 33(0) | 0(0) | 0(0) |
| u_fifo | 28(28) | 0(0) | 0(0) | 33(33) | 0(0) | 0(0) |
| i_apb_cdc | 89(89) | 0(0) | 0(0) | 234(234) | 0(0) | 0(0) |
| u_ctrl_wrap | 10518(0) | 432(0) | 1298(0) | 5832(0) | 0(0) | 21(0) |
| u_controller | 10518(10518) | 432(432) | 1298(1298) | 5832(5832) | 0(0) | 21(21) |
| u_lp4mem | 155(69) | 0(0) | 20(10) | 88(11) | 29(0) | 0(0) |
| CA_GRP_ENA.u_ca_grp | 15(15) | 0(0) | 10(10) | 24(24) | 9(9) | 0(0) |
| u1_clock_sync | 70(0) | 0(0) | 0(0) | 53(0) | 0(0) | 0(0) |
| u1_mem_sync | 70(70) | 0(0) | 0(0) | 53(53) | 0(0) | 0(0) |
| u_dq_dqs_dm | 0(0) | 0(0) | 0(0) | 0(0) | 20(20) | 0(0) |
| u_pll | 1(1) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| u_tragen | 3687(20) | 228(0) | 564(0) | 2815(0) | 10(0) | 16(0) |
| IMPL.sysmem0_inst | 157(0) | 0(0) | 16(0) | 55(0) | 0(0) | 16(0) |
| lscc_sys_mem_inst | 157(0) | 0(0) | 16(0) | 55(0) | 0(0) | 16(0) |
| bridge_s0.bridge_s0 | 10(10) | 0(0) | 0(0) | 6(6) | 0(0) | 0(0) |
| bridge_s1.bridge_s1 | 143(143) | 0(0) | 16(16) | 49(49) | 0(0) | 0(0) |
| u_lscc_mem0 | 4(0) | 0(0) | 0(0) | 0(0) | 0(0) | 16(0) |
| lifcl_LATG1.ebr.dp.LIFCL.u_mem | 4(0) | 0(0) | 0(0) | 0(0) | 0(0) | 16(0) |
| mem_main | 4(0) | 0(0) | 0(0) | 0(0) | 0(0) | 16(0) |
| uinst_0 | 4(0) | 0(0) | 0(0) | 0(0) | 0(0) | 16(0) |
| prim.NON_MIX.xADDR[0].xDATA[0].mem_file.u_mem0 | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| prim.NON_MIX.xADDR[0].xDATA[10].mem_file.u_mem0 | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| prim.NON_MIX.xADDR[0].xDATA[11].mem_file.u_mem0 | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| prim.NON_MIX.xADDR[0].xDATA[12].mem_file.u_mem0 | 1(1) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| prim.NON_MIX.xADDR[0].xDATA[13].mem_file.u_mem0 | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| prim.NON_MIX.xADDR[0].xDATA[14].mem_file.u_mem0 | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| prim.NON_MIX.xADDR[0].xDATA[15].mem_file.u_mem0 | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| prim.NON_MIX.xADDR[0].xDATA[1].mem_file.u_mem0 | 1(1) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| prim.NON_MIX.xADDR[0].xDATA[2].mem_file.u_mem0 | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| prim.NON_MIX.xADDR[0].xDATA[3].mem_file.u_mem0 | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| prim.NON_MIX.xADDR[0].xDATA[4].mem_file.u_mem0 | 1(1) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| prim.NON_MIX.xADDR[0].xDATA[5].mem_file.u_mem0 | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| prim.NON_MIX.xADDR[0].xDATA[6].mem_file.u_mem0 | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| prim.NON_MIX.xADDR[0].xDATA[7].mem_file.u_mem0 | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| prim.NON_MIX.xADDR[0].xDATA[8].mem_file.u_mem0 | 1(1) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| prim.NON_MIX.xADDR[0].xDATA[9].mem_file.u_mem0 | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) | 1(1) |
| ahbl0_inst | 88(0) | 0(0) | 0(0) | 6(0) | 0(0) | 0(0) |
| lscc_ahbl_interconnect_inst | 88(0) | 0(0) | 0(0) | 6(0) | 0(0) | 0(0) |
| ahb_lite_bus.u_lscc_ahbl_bus | 88(0) | 0(0) | 0(0) | 6(0) | 0(0) | 0(0) |
| u_lscc_ahbl_decoder | 14(13) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| genblk1[1].u_lscc_ahbl_decoder_sel | 1(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| genblk1[0].u_lscc_ahbl_decoder_comp | 1(1) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| u_lscc_ahbl_default_slv | 2(2) | 0(0) | 0(0) | 2(2) | 0(0) | 0(0) |
| u_lscc_ahbl_multiplexor | 72(72) | 0(0) | 0(0) | 4(4) | 0(0) | 0(0) |
| ahbl2apb0_inst | 291(0) | 0(0) | 0(0) | 106(0) | 0(0) | 0(0) |
| lscc_ahbl2apb_inst | 291(291) | 0(0) | 0(0) | 106(106) | 0(0) | 0(0) |
| apb0_inst | 64(0) | 0(0) | 0(0) | 5(0) | 0(0) | 0(0) |
| lscc_apb_interconnect_inst | 64(0) | 0(0) | 0(0) | 5(0) | 0(0) | 0(0) |
| apb_bus.u_lscc_apb_bus | 64(0) | 0(0) | 0(0) | 5(0) | 0(0) | 0(0) |
| u_lscc_apb_decoder | 15(5) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| genblk1[1].u_lscc_apb_decoder_sel | 1(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| genblk1[0].u_lscc_apb_decoder_comp | 1(1) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| genblk1[3].u_lscc_apb_decoder_sel | 9(0) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| genblk1[0].u_lscc_apb_decoder_comp | 9(9) | 0(0) | 0(0) | 0(0) | 0(0) | 0(0) |
| u_lscc_apb_multiplexor | 49(49) | 0(0) | 0(0) | 5(5) | 0(0) | 0(0) |
| axi_tragen_inst | 1755(0) | 36(0) | 360(0) | 1653(0) | 0(0) | 0(0) |
| u_axi_m_csr | 576(576) | 0(0) | 10(10) | 717(717) | 0(0) | 0(0) |
| u_axi_m_rd | 565(340) | 18(0) | 90(90) | 390(151) | 0(0) | 0(0) |
| LFSR16[0].u_wdata_gen | 17(17) | 0(0) | 0(0) | 16(16) | 0(0) | 0(0) |
| LFSR16[1].u_wdata_gen | 17(17) | 0(0) | 0(0) | 16(16) | 0(0) | 0(0) |
| LFSR16[2].u_wdata_gen | 17(17) | 0(0) | 0(0) | 16(16) | 0(0) | 0(0) |
| LFSR16[3].u_wdata_gen | 17(17) | 0(0) | 0(0) | 16(16) | 0(0) | 0(0) |
| LFSR16[4].u_wdata_gen | 17(17) | 0(0) | 0(0) | 16(16) | 0(0) | 0(0) |
| LFSR16[5].u_wdata_gen | 17(17) | 0(0) | 0(0) | 16(16) | 0(0) | 0(0) |
| LFSR16[6].u_wdata_gen | 17(17) | 0(0) | 0(0) | 16(16) | 0(0) | 0(0) |
| LFSR16[7].u_wdata_gen | 17(17) | 0(0) | 0(0) | 16(16) | 0(0) | 0(0) |
| u_a2d_fifo | 36(0) | 18(0) | 0(0) | 58(0) | 0(0) | 0(0) |
| lscc_fifo_inst | 36(0) | 18(0) | 0(0) | 58(0) | 0(0) | 0(0) |
| fifo0 | 36(0) | 18(0) | 0(0) | 58(0) | 0(0) | 0(0) |
| _FABRIC.u_fifo | 36(36) | 18(18) | 0(0) | 58(58) | 0(0) | 0(0) |
| u_araddr_gen | 33(33) | 0(0) | 0(0) | 32(32) | 0(0) | 0(0) |
| u_ctrl_gen | 20(20) | 0(0) | 0(0) | 21(21) | 0(0) | 0(0) |
| u_axi_m_wr | 449(235) | 18(0) | 90(90) | 371(132) | 0(0) | 0(0) |
| LFSR16[0].u_wdata_gen | 17(17) | 0(0) | 0(0) | 16(16) | 0(0) | 0(0) |
| LFSR16[1].u_wdata_gen | 17(17) | 0(0) | 0(0) | 16(16) | 0(0) | 0(0) |
| LFSR16[2].u_wdata_gen | 17(17) | 0(0) | 0(0) | 16(16) | 0(0) | 0(0) |
| LFSR16[3].u_wdata_gen | 17(17) | 0(0) | 0(0) | 16(16) | 0(0) | 0(0) |
| LFSR16[4].u_wdata_gen | 17(17) | 0(0) | 0(0) | 16(16) | 0(0) | 0(0) |
| LFSR16[5].u_wdata_gen | 17(17) | 0(0) | 0(0) | 16(16) | 0(0) | 0(0) |
| LFSR16[6].u_wdata_gen | 17(17) | 0(0) | 0(0) | 16(16) | 0(0) | 0(0) |
| LFSR16[7].u_wdata_gen | 17(17) | 0(0) | 0(0) | 16(16) | 0(0) | 0(0) |
| u_a2d_fifo | 32(0) | 18(0) | 0(0) | 58(0) | 0(0) | 0(0) |
| lscc_fifo_inst | 32(0) | 18(0) | 0(0) | 58(0) | 0(0) | 0(0) |
| fifo0 | 32(0) | 18(0) | 0(0) | 58(0) | 0(0) | 0(0) |
| _FABRIC.u_fifo | 32(32) | 18(18) | 0(0) | 58(58) | 0(0) | 0(0) |
| u_awaddr_gen | 32(32) | 0(0) | 0(0) | 32(32) | 0(0) | 0(0) |
| u_ctrl_gen | 14(14) | 0(0) | 0(0) | 21(21) | 0(0) | 0(0) |
| u_axi_perf_calc | 165(165) | 0(0) | 170(170) | 175(175) | 0(0) | 0(0) |
| cpu0_inst | 890(5) | 192(0) | 152(18) | 640(22) | 0(0) | 0(0) |
| i_cpu | 885(853) | 192(192) | 134(134) | 618(587) | 0(0) | 0(0) |
| IBusSimplePlugin_rspJoin_rspBuffer_c | 32(32) | 0(0) | 0(0) | 31(31) | 0(0) | 0(0) |
| gpio0_inst | 124(0) | 0(0) | 0(0) | 121(0) | 10(0) | 0(0) |
| lscc_gpio_inst | 124(0) | 0(0) | 0(0) | 121(0) | 10(0) | 0(0) |
| LxxNX.lscc_gpio_lmmi_0 | 89(89) | 0(0) | 0(0) | 90(90) | 10(10) | 0(0) |
| genblk2.lscc_apb2lmmi_0 | 35(35) | 0(0) | 0(0) | 31(31) | 0(0) | 0(0) |
| memc_apb_inst | 2(0) | 0(0) | 0(0) | 79(0) | 0(0) | 0(0) |
| lscc_apb_feedthrough_inst | 2(2) | 0(0) | 0(0) | 79(79) | 0(0) | 0(0) |
| uart0_inst | 296(0) | 0(0) | 36(0) | 150(0) | 0(0) | 0(0) |
| lscc_uart_inst | 296(0) | 0(0) | 36(0) | 150(0) | 0(0) | 0(0) |
| u_intface | 37(37) | 0(0) | 0(0) | 50(50) | 0(0) | 0(0) |
| u_rxcver | 117(117) | 0(0) | 18(18) | 57(57) | 0(0) | 0(0) |
| u_txmitt | 142(142) | 0(0) | 18(18) | 43(43) | 0(0) | 0(0) |