    Timing Report
    Lattice Timing Report -  Setup  and Hold, Version Radiant Software (64-bit) 2023.2.0.38.1  Patch Version(s) 20248

    Mon Mar 18 12:44:26 2024

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.

    Command line:    timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -sp 9_High-Performance_1.0V -hsp m -pwrprd -html -rpt lpddr4_axi_201_impl_1.twr lpddr4_axi_201_impl_1.udb -gui -msgset /media/d480/GitHubProjects/TssTechnique/TssProjects/TssSemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/promote.xml

    -------------------------------------------
    Design:          eval_top
    Family:          LFCPNX
    Device:          LFCPNX-100
    Package:         BBG484
    Performance:     9_High-Performance_1.0V
    Package Status:                     Final          Version 16
    Performance Hardware Data Status :   Final Version 3.9
    -------------------------------------------

    =====================================================================
                        Table of Contents
    =====================================================================
        1  Timing Overview
            1.1  SDC Constraints
            1.2  Constraint Coverage
            1.3  Overall Summary
            1.4  Unconstrained Report
            1.5  Combinational Loop
        2  Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees
            2.1  Clock Summary
            2.2  Endpoint slacks
            2.3  Detailed Report
        3  Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees
            3.1  Clock Summary
            3.2  Endpoint slacks
            3.3  Detailed Report
        4  Hold at Speed Grade m Corner at 0 Degrees
            4.1  Endpoint slacks
            4.2  Detailed Report

    =====================================================================
                        End of Table of Contents
    =====================================================================

    1  Timing Overview

    1.1  SDC Constraints

    create_clock -name {osc_clk_90} -period 11.1111 [get_pins {osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT }]
    create_generated_clock -name {out_clk1_c} -source [get_pins {ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -divide_by 1 [get_pins {ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS }]
    create_generated_clock -name {clk_w} -source [get_pins {ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 3 -divide_by 2 [get_pins {ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP }]
    create_generated_clock -name {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w} -source [get_pins {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 16 -divide_by 3 [get_pins {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS }]
    create_generated_clock -name {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w} -source [get_pins {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -divide_by 1 [get_pins {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP }]
    create_generated_clock -name {sclk_o} -source [get_pins {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN}] -divide_by 4 [get_pins {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT }]
    create_clock -name {pll_refclk_i} -period 10 [get_ports pll_refclk_i]
    set_false_path -to [get_pins */lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/DQSBUF*.VREF.u0_DQSBUF.DQSBUFA_inst/RST]
    set_false_path -to [get_pins */lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVRST]
    set_false_path -to [get_pins */lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u1_mem_sync/dll_rst_o*.ff_inst/LSR]
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u1_mem_sync/ddr_clk_sel_i_r*.ff_inst/Q] -to [get_pins */lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u1_mem_sync/ddr_clk_sel_d1_r*.ff_inst/DF] -datapath_only 2.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u1_mem_sync/ddr_clk_update_i_r*.ff_inst/Q] -to [get_pins */lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u1_mem_sync/sync_clk_update_sr0*.ff_inst/DF] -datapath_only 2.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u1_mem_sync/friz2init_tgle_r*.ff_inst/Q] -to [get_pins */lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u1_mem_sync/friz2init_tgle_sr0*.ff_inst/DF] -datapath_only 2.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u1_mem_sync/ready_r*.ff_inst/Q] -to [get_pins */lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u1_mem_sync/ready_r0*.ff_inst/DF] -datapath_only 5
    set_false_path -to [get_pins */lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u1_mem_sync/dll_lock_i_r*.ff_inst/DF]
    set_false_path -to [get_pins */lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u1_mem_sync/lock_d1*.ff_inst/DF]
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/i_apb_cdc/m_m2s_pend0_r*.ff_inst/Q] -to [get_pins */lscc_lpddr4_mc_inst/i_apb_cdc/s_m2s_b0_r0*.ff_inst/DF] -datapath_only 2.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/i_apb_cdc/m_m2s_pend1_r*.ff_inst/Q] -to [get_pins */lscc_lpddr4_mc_inst/i_apb_cdc/s_m2s_b1_r0*.ff_inst/DF] -datapath_only 2.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/i_apb_cdc/m_m2s_rdata_pend_r*.ff_inst/Q] -to [get_pins */lscc_lpddr4_mc_inst/i_apb_cdc/s_m2s_rdata_r0*.ff_inst/DF] -datapath_only 2.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/i_apb_cdc/s_s2m_pend0_r*.ff_inst/Q] -to [get_pins */lscc_lpddr4_mc_inst/i_apb_cdc/m_s2m_b0_r0*.ff_inst/DF] -datapath_only 2.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/i_apb_cdc/s_s2m_pend1_r*.ff_inst/Q] -to [get_pins */lscc_lpddr4_mc_inst/i_apb_cdc/m_s2m_b1_r0*.ff_inst/DF] -datapath_only 2.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/s_phy_ready_r*.ff_inst/Q] -to [get_pins */lscc_lpddr4_mc_inst/p_phy_ready_r1*.ff_inst/DF] -datapath_only 2.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/i_apb_cdc/s_buf*.ff_inst/Q] -to [get_pins */lscc_lpddr4_mc_inst/i_apb_cdc/apb_m0_pwdata_mst_o*.ff_inst/DF] -datapath_only 4.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/i_apb_cdc/s_buf*.ff_inst/Q] -to [get_pins */lscc_lpddr4_mc_inst/i_apb_cdc/apb_m0_paddr_mst_o*.ff_inst/DF] -datapath_only 4.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/i_apb_cdc/s_buf*.ff_inst/Q] -to [get_pins */lscc_lpddr4_mc_inst/i_apb_cdc/apb_m0_pwrite_mst_o*.ff_inst/DF] -datapath_only 4.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/i_apb_cdc/m_m2s_prdata_r*.ff_inst/Q] -to [get_pins */lscc_lpddr4_mc_inst/i_apb_cdc/apb_s0_prdata_slv_o*.ff_inst/DF] -datapath_only 4.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wr_grey_sync_r*/Q] -to [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_r*/DF] -datapath_only 2.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wr_grey_sync_r*/Q] -to [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_r*/DF] -datapath_only 2.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wr_grey_sync_r*/Q] -to [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync1_r*/DF] -datapath_only 2.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rd_grey_sync_r*/Q] -to [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_r*/DF] -datapath_only 2.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rd_grey_sync_r*/Q] -to [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_r*/DF] -datapath_only 2.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rd_grey_sync_r*/Q] -to [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync1_r*/DF] -datapath_only 2.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wr_addr_r*/Q] -datapath_only 4.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wr_addr_r*/Q] -datapath_only 4.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wr_addr_r*/Q] -datapath_only 4.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/EBR_CTRL*.ASYNC.u_enable_bus_sync/toggle_r*.ff_inst/Q] -to [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/EBR_CTRL*.ASYNC.u_enable_bus_sync/sync_toggle_r1*.ff_inst/DF] -datapath_only 2.5
    set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/*ebr_not_empty_r*.ff_inst/Q] -to [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/EBR_CTRL*.ASYNC.u_not_empty_sync/data_0*.ff_inst/DF] -datapath_only 2.5
    set_false_path -to [get_pins */lscc_lpddr4_mc_inst/arst_n*.ff_inst/LSR]
    set_false_path -to [get_pins */lscc_lpddr4_mc_inst/phy_srst_n*.ff_inst/LSR]
    set_false_path -to [get_pins */lscc_lpddr4_mc_inst/srst_n*.ff_inst/LSR]
    set_false_path -to [get_pins */lscc_lpddr4_mc_inst/p_cpu_rst_n_r*.ff_inst/LSR]
    set_false_path -to [get_pins */lscc_lpddr4_mc_inst/sync_rst_n*.ff_inst/LSR]
    set_false_path -to [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_lpddr4_mc_rd_rtrn_ebr_inst/lscc_ram_dp_inst/mem_main/*.u_mem0/*PDP16K_MODE_inst/RST]
    set_false_path -from [get_pins */lscc_lpddr4_mc_inst/wr_dir_r*.ff_inst/Q] -to [get_pins */lscc_lpddr4_mc_inst/wr_cout_r*.ff_inst/DF]
    set_false_path -from [get_pins */lscc_lpddr4_mc_inst/rd_dir_r*.ff_inst/Q] -to [get_pins */lscc_lpddr4_mc_inst/rd_cout_r*.ff_inst/DF]
    set_false_path -to [get_pins areset_n*.ff_inst/LSR]
    set_false_path -to [get_pins prst_n*.ff_inst/LSR]
    set_false_path -to [get_pins sreset_n*.ff_inst/LSR]
    set_false_path -to [get_pins u_tragen/axi_tragen_inst/u_axi_m_csr/cdc_r1_wr_start_*/DF]
    set_false_path -to [get_pins u_tragen/axi_tragen_inst/u_axi_m_csr/cdc_r1_wr_txn_done_*/DF]
    set_false_path -to [get_pins u_tragen/axi_tragen_inst/u_axi_m_csr/cfg_*/DF]
    set_false_path -to [get_pins u_tragen/axi_tragen_inst/u_axi_m_csr/cdc_r1_*/DF]
    set_max_delay -from [get_pins u_tragen/axi_tragen_inst/u_axi_m_csr/p2a_*/Q] -datapath_only 5
    set_max_delay -from [get_pins u_tragen/axi_tragen_inst/u_axi_m_csr/a2p_*/Q] -datapath_only 5
    set_max_delay -from [get_pins u_tragen/axi_tragen_inst/u_axi_m_csr/csr_*/Q] -datapath_only 5
    set_max_delay -from [get_pins u_tragen/axi_tragen_inst/u_axi_m_csr/a2p_*/Q] -datapath_only 7.5
    set_false_path -to [get_pins u_tragen/axi_tragen_inst/u_axi_m_csr/gen_in*.ff_inst/DF]
    set_false_path -to [get_pins u_tragen/axi_tragen_inst/u_axi_m_csr/total_num_wr_rd_r*/DF]
    set_false_path -to [get_pins u_tragen/axi_tragen_inst/u_axi_m_csr/duration_cntr_status_sclk_r*/DF]
    set_false_path -to [get_pins u_tragen/axi_tragen_inst/u_axi_m_csr/duration_cntr_status_aclk_r*/DF]
    set_false_path -to [get_pins u_tragen/axi_tragen_inst/u_axi_perf_calc/*a2s_duration_cntr_en_r1*/DF]
    set_false_path -from [get_pins u_tragen/uart0_inst/lscc_uart_inst/u_txmitt/*tx_output*/Q]
    set_false_path -to [get_pins u_tragen/uart0_inst/lscc_uart_inst/u_rxcver/sin*/D*]
    set_false_path -from [get_pins */LED_array_i*/Q]
    set_false_path -to [get_ports LED*]
    set_false_path -to [get_pins s2p_r1_trn_done*.ff_inst/DF]
    set_false_path -from [get_pins */lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/DQ*.*/DOUT]
    set_false_path -from [get_pins */lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/DQ*.*/TOUT]
    set_false_path -from [get_pins */lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/DMI*.*/DOUT]
    set_false_path -from [get_pins */lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/DMI*.*/TOUT]

    1.2  Constraint Coverage

    Constraint Coverage: 99.7616%

    1.3  Overall Summary

     Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees    Timing Errors: 259 endpoints;  Total Negative Slack: 547.603 ns
     Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees     Timing Errors: 259 endpoints;  Total Negative Slack: 576.262 ns
     Hold at Speed Grade m Corner at 0 Degrees                            Timing Errors: 19 endpoints;  Total Negative Slack: 8.932 ns

    1.4  Unconstrained Report

    1.4.1  Unconstrained Start/End Points

    Clocked but unconstrained timing start points
    -------------------------------------------------------------------
            Listing 10 Start Points         |           Type
    -------------------------------------------------------------------
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/reset_n_o.ff_inst/Q
                                            |          No required time
    {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/CK[0].u_CK_t_DLA/Z   u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/CK[0].CK_X4.u_CK_t/Q}
                                            |          No required time
    {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/CKE[0].u_CKE_DLA/Z   u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/CKE[0].CKE_X4.u_CKE/Q}
                                            |          No required time
    {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/CS[0].u_CS_DLA/Z   u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/CS[0].CS_X4.u_CS/Q}
                                            |          No required time
    {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/CA[0].u_CA_DLA/Z   u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/CA[0].CA_X4.u_CA/Q}
                                            |          No required time
    {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/CA[1].u_CA_DLA/Z   u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/CA[1].CA_X4.u_CA/Q}
                                            |          No required time
    {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/CA[2].u_CA_DLA/Z   u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/CA[2].CA_X4.u_CA/Q}
                                            |          No required time
    {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/CA[3].u_CA_DLA/Z   u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/CA[3].CA_X4.u_CA/Q}
                                            |          No required time
    {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/CA[4].u_CA_DLA/Z   u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/CA[4].CA_X4.u_CA/Q}
                                            |          No required time
    {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/CA[5].u_CA_DLA/Z   u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/CA[5].CA_X4.u_CA/Q}
                                            |          No required time
    -------------------------------------------------------------------
                                            |
    Number of unconstrained timing start po |
    ints                                    |                        11
                                            |
    -------------------------------------------------------------------

    Clocked but unconstrained timing end points
    -------------------------------------------------------------------
             Listing 10 End Points          |           Type
    -------------------------------------------------------------------
    u_mem/lscc_lpddr4_mc_inst/u_ctrl_wrap/u_controller/secured_instance_272_0/secured_instance_271_5/secured_instance_258_533/DF
                                            |           No arrival time
    u_mem/lscc_lpddr4_mc_inst/u_ctrl_wrap/u_controller/secured_instance_272_0/secured_instance_271_5/secured_instance_258_534/DF
                                            |           No arrival time
    u_mem/lscc_lpddr4_mc_inst/u_ctrl_wrap/u_controller/secured_instance_272_0/secured_instance_271_5/secured_instance_258_535/DF
                                            |           No arrival time
    u_mem/lscc_lpddr4_mc_inst/u_ctrl_wrap/u_controller/secured_instance_272_0/secured_instance_271_5/secured_instance_258_536/DF
                                            |           No arrival time
    u_mem/lscc_lpddr4_mc_inst/u_ctrl_wrap/u_controller/secured_instance_272_0/secured_instance_271_5/secured_instance_258_537/DF
                                            |           No arrival time
    u_mem/lscc_lpddr4_mc_inst/u_ctrl_wrap/u_controller/secured_instance_272_0/secured_instance_271_5/secured_instance_258_538/DF
                                            |           No arrival time
    u_mem/lscc_lpddr4_mc_inst/u_ctrl_wrap/u_controller/secured_instance_272_0/secured_instance_271_5/secured_instance_258_539/DF
                                            |           No arrival time
    u_mem/lscc_lpddr4_mc_inst/u_ctrl_wrap/u_controller/secured_instance_272_0/secured_instance_271_5/secured_instance_258_540/DF
                                            |           No arrival time
    u_mem/lscc_lpddr4_mc_inst/u_ctrl_wrap/u_controller/secured_instance_272_0/secured_instance_271_5/secured_instance_258_541/DF
                                            |           No arrival time
    u_mem/lscc_lpddr4_mc_inst/u_ctrl_wrap/u_controller/secured_instance_272_0/secured_instance_271_5/secured_instance_258_542/DF
                                            |           No arrival time
    -------------------------------------------------------------------
                                            |
    Number of unconstrained timing end poin |
    ts                                      |                        16
                                            |
    -------------------------------------------------------------------

    1.4.2  Start/End Points Without Timing Constraints

    I/O ports without constraint
    ----------------------------
    Possible constraints to use on I/O ports are:
    set_input_delay,
    set_output_delay,
    set_max_delay,
    create_clock,
    create_generated_clock,
    ...

    -------------------------------------------------------------------
         Listing 10 Start or End Points     |           Type
    -------------------------------------------------------------------
    ddr_dq_io[0]                            |                     input
    ddr_dq_io[1]                            |                     input
    ddr_dq_io[2]                            |                     input
    ddr_dq_io[3]                            |                     input
    ddr_dq_io[4]                            |                     input
    ddr_dq_io[5]                            |                     input
    ddr_dq_io[6]                            |                     input
    ddr_dq_io[7]                            |                     input
    ddr_dq_io[8]                            |                     input
    ddr_dq_io[9]                            |                     input
    -------------------------------------------------------------------
                                            |
    Number of I/O ports without constraint  |                        31
                                            |
    -------------------------------------------------------------------

    Nets without clock definition
    Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s).
    --------------------------------------------------
    There is no instance satisfying reporting criteria

    1.5  Combinational Loop

    None

    2  Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees
    2.1  Clock Summary
    2.1.1 Clock "sclk_o"

    create_generated_clock -name {sclk_o} -source [get_pins {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN}] -divide_by 4 [get_pins {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT }]

    Single Clock Domain
    -------------------------------------------------------------------------------------------------------
                  Clock sclk_o              |                    |       Period       |     Frequency
    -------------------------------------------------------------------------------------------------------
     From sclk_o                            |             Target |           7.500 ns |        133.333 MHz
                                            | Actual (all paths) |           6.657 ns |        150.218 MHz
    u_mem/lscc_lpddr4_mc_inst/u_ctrl_wrap/u_controller/secured_instance_272_1/secured_instance_209_1/secured_instance_208_142/secured_instance_207_0/secured_instance_206_0/secured_instance_205_0/secured_instance_204_0/CLKW (MPW)
                                            |   (50% duty cycle) |           2.942 ns |        339.905 MHz
    -------------------------------------------------------------------------------------------------------

    Clock Domain Crossing
    ------------------------------------------------------------------------------------------------------
                  Clock sclk_o              |   Worst Time Between Edges   |           Comment
    ------------------------------------------------------------------------------------------------------
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w
                                            |                         ---- |                      No path
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w
                                            |                     1.875 ns |             slack = 3.610 ns
     From clk_w                             |                     0.092 ns |            slack = -2.771 ns
     From out_clk1_c                        |                         ---- |                      No path
     From osc_clk_90                        |                         ---- |                      No path
     From pll_refclk_i                      |                         ---- |                      No path
    ------------------------------------------------------------------------------------------------------
    2.1.2 Clock "u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w"

    create_generated_clock -name {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w} -source [get_pins {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -divide_by 1 [get_pins {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP }]

    Single Clock Domain
    ---------------------------------------------------------------------------------------------------------------------
    Clock u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w|                    |       Period       |     Frequency
    ---------------------------------------------------------------------------------------------------------------------
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w|             Target |          10.000 ns |        100.000 MHz
                                                          | Actual (all paths) |               ---- |               ----
    ---------------------------------------------------------------------------------------------------------------------

    Clock Domain Crossing
    --------------------------------------------------------------------------------------------------------------------
    Clock u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w|   Worst Time Between Edges   |           Comment
    --------------------------------------------------------------------------------------------------------------------
     From sclk_o                                          |                         ---- |                      No path
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w       |                         ---- |                      No path
     From clk_w                                           |                         ---- |                      No path
     From out_clk1_c                                      |                         ---- |                      No path
     From osc_clk_90                                      |                         ---- |                      No path
     From pll_refclk_i                                    |                         ---- |                      No path
    --------------------------------------------------------------------------------------------------------------------
    2.1.3 Clock "u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w"

    create_generated_clock -name {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w} -source [get_pins {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 16 -divide_by 3 [get_pins {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS }]

    Single Clock Domain
    --------------------------------------------------------------------------------------------------------------
    Clock u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w|                    |       Period       |     Frequency
    --------------------------------------------------------------------------------------------------------------
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w|             Target |           1.875 ns |        533.333 MHz
                                                   | Actual (all paths) |           1.874 ns |        533.618 MHz
    {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/DQS[0].DQS_X4.u_ODDRX4DQS/WRCLK   u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/TS[0].TS_X4.u_TSHX4DQS/WRCLK} (MPW)
                                                   |   (50% duty cycle) |           1.874 ns |        533.618 MHz
    --------------------------------------------------------------------------------------------------------------

    Clock Domain Crossing
    -------------------------------------------------------------------------------------------------------------
    Clock u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w|   Worst Time Between Edges   |           Comment
    -------------------------------------------------------------------------------------------------------------
     From sclk_o                                   |                     1.875 ns |             slack = 2.861 ns
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w
                                                   |                         ---- |                      No path
     From clk_w                                    |                         ---- |                      No path
     From out_clk1_c                               |                         ---- |                      No path
     From osc_clk_90                               |                         ---- |                      No path
     From pll_refclk_i                             |                         ---- |                      No path
    -------------------------------------------------------------------------------------------------------------
    2.1.4 Clock "clk_w"

    create_generated_clock -name {clk_w} -source [get_pins {ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 3 -divide_by 2 [get_pins {ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP }]

    Single Clock Domain
    -------------------------------------------------------------------------------------------------------
                  Clock clk_w               |                    |       Period       |     Frequency
    -------------------------------------------------------------------------------------------------------
     From clk_w                             |             Target |           7.407 ns |        135.000 MHz
                                            | Actual (all paths) |           7.314 ns |        136.724 MHz
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_lpddr4_mc_rd_rtrn_ebr_inst/lscc_ram_dp_inst/mem_main/NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[3].no_init.u_mem0/LIFCL_MEM.pdp16k.PDP16K_MODE_inst/CLKR (MPW)
                                            |   (50% duty cycle) |           2.942 ns |        339.905 MHz
    -------------------------------------------------------------------------------------------------------

    Clock Domain Crossing
    ------------------------------------------------------------------------------------------------------
                  Clock clk_w               |   Worst Time Between Edges   |           Comment
    ------------------------------------------------------------------------------------------------------
     From sclk_o                            |                     0.092 ns |            slack = -0.361 ns
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w
                                            |                         ---- |                      No path
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w
                                            |                         ---- |                      No path
     From out_clk1_c                        |                         ---- |                      No path
     From osc_clk_90                        |                         ---- |                      No path
     From pll_refclk_i                      |                         ---- |                      No path
    ------------------------------------------------------------------------------------------------------
    2.1.5 Clock "out_clk1_c"

    create_generated_clock -name {out_clk1_c} -source [get_pins {ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -divide_by 1 [get_pins {ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS }]

    Single Clock Domain
    -------------------------------------------------------------------------------------------------------
                Clock out_clk1_c            |                    |       Period       |     Frequency
    -------------------------------------------------------------------------------------------------------
     From out_clk1_c                        |             Target |          11.111 ns |         90.000 MHz
                                            | Actual (all paths) |          10.437 ns |         95.813 MHz
    out_clk1_pad.bb_inst/B (MPW)            |   (50% duty cycle) |           5.000 ns |        200.000 MHz
    -------------------------------------------------------------------------------------------------------

    Clock Domain Crossing
    ------------------------------------------------------------------------------------------------------
                Clock out_clk1_c            |   Worst Time Between Edges   |           Comment
    ------------------------------------------------------------------------------------------------------
     From sclk_o                            |                         ---- |                      No path
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w
                                            |                         ---- |                      No path
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w
                                            |                         ---- |                      No path
     From clk_w                             |                         ---- |                      No path
     From osc_clk_90                        |                         ---- |                      No path
     From pll_refclk_i                      |                         ---- |                      No path
    ------------------------------------------------------------------------------------------------------
    2.1.6 Clock "osc_clk_90"

    create_clock -name {osc_clk_90} -period 11.1111 [get_pins {osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT }]

    Single Clock Domain
    -------------------------------------------------------------------------------------------------------
                Clock osc_clk_90            |                    |       Period       |     Frequency
    -------------------------------------------------------------------------------------------------------
     From osc_clk_90                        |             Target |          11.111 ns |         90.000 MHz
                                            | Actual (all paths) |           4.354 ns |        229.674 MHz
    osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT (MPW)
                                            |   (50% duty cycle) |           4.354 ns |        229.674 MHz
    -------------------------------------------------------------------------------------------------------

    Clock Domain Crossing
    ------------------------------------------------------------------------------------------------------
                Clock osc_clk_90            |   Worst Time Between Edges   |           Comment
    ------------------------------------------------------------------------------------------------------
     From sclk_o                            |                         ---- |                      No path
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w
                                            |                         ---- |                      No path
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w
                                            |                         ---- |                      No path
     From clk_w                             |                         ---- |                      No path
     From out_clk1_c                        |                         ---- |                      No path
     From pll_refclk_i                      |                         ---- |                      No path
    ------------------------------------------------------------------------------------------------------
    2.1.7 Clock "pll_refclk_i"

    create_clock -name {pll_refclk_i} -period 10 [get_ports pll_refclk_i]

    Single Clock Domain
    -------------------------------------------------------------------------------------------------------
               Clock pll_refclk_i           |                    |       Period       |     Frequency
    -------------------------------------------------------------------------------------------------------
     From pll_refclk_i                      |             Target |          10.000 ns |        100.000 MHz
                                            | Actual (all paths) |           1.874 ns |        533.618 MHz
    pll_refclk_i_pad.bb_inst/B (MPW)        |   (50% duty cycle) |           1.874 ns |        533.618 MHz
    -------------------------------------------------------------------------------------------------------

    Clock Domain Crossing
    ------------------------------------------------------------------------------------------------------
               Clock pll_refclk_i           |   Worst Time Between Edges   |           Comment
    ------------------------------------------------------------------------------------------------------
     From sclk_o                            |                         ---- |                      No path
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w
                                            |                         ---- |                      No path
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w
                                            |                         ---- |                      No path
     From clk_w                             |                         ---- |                      No path
     From out_clk1_c                        |                         ---- |                      No path
     From osc_clk_90                        |                         ---- |                      No path
    ------------------------------------------------------------------------------------------------------

    2.2  Endpoint slacks
    -------------------------------------------------------
              Listing 10 End Points          |    Slack
    -------------------------------------------------------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_valid_c.ff_inst/DF
                                             |   -2.771 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_req_valid_c.ff_inst/DF
                                             |   -2.731 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_data_last.ff_inst/DF
                                             |   -2.727 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i42.ff_inst/DF
                                             |   -2.247 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i84.ff_inst/DF
                                             |   -2.247 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i82.ff_inst/DF
                                             |   -2.247 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i48.ff_inst/DF
                                             |   -2.247 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i46.ff_inst/DF
                                             |   -2.247 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i56.ff_inst/DF
                                             |   -2.247 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i54.ff_inst/DF
                                             |   -2.247 ns
    -------------------------------------------------------
                                             |
    Setup # of endpoints with negative slack:|         259
                                             |
    -------------------------------------------------------

    2.3  Detailed Report

    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Detail report of critical paths

    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

     +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
                        Detailed Report for timing paths
     +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

     ++++Path 1  ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WDO0  (SLICE_R56C111C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_valid_c.ff_inst/DF  (SLICE_R54C111D)
    Source Clock     : clk_w (R)
    Destination Clock: sclk_o (R)
    Logic Level      : 3
    Delay Ratio      : 20.4% (route), 79.6% (logic)
    Clock Skew       : -1.391 ns
    Setup Constraint : 0.092 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -2.771 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_8.SLICE_2787/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":2.559,
            "delay":2.559
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":2.559,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.169,
            "delay":-2.390
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.560,
            "delay":2.391
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.560,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY         0.000                  0.000  2
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY             2.559                  2.559  2
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                           0.000                  2.559  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                          -2.390                  0.169  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY             2.391                  2.560  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WCK
                                                                                   CLOCK PIN             0.000                  2.560  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WDO0",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_8.SLICE_2787/WDO0"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_valid_c.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11550/DI0"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_8.SLICE_2787/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WDO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_8.SLICE_2787/WDO0"
            },
            "arrive":2.560,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.wdo0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_8.wdo0"
            },
            "arrive":2.560,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.dpram_inst_0/DI0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2788/WDI0"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.dpram_inst_0/DO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2788/F0"
            },
            "arrive":3.566,
            "delay":1.006
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[128]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.out_raw[128]"
            },
            "arrive":3.878,
            "delay":0.312
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/i392_4_lut_4_lut/C",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11550/C0"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/i392_4_lut_4_lut/Z",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11550/F0"
            },
            "arrive":4.091,
            "delay":0.213
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_valid_N_13318",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.wr_valid_N_13318"
            },
            "arrive":4.091,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":4.091,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WDO0
                                              SLICE_R56C111C                       CLKTOQWD_DEL          0.000                  2.560  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.wdo0
                                                                                   NET DELAY             0.000                  2.560  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.dpram_inst_0/DI0->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.dpram_inst_0/DO0
                                              SLICE_R56C111A                       QWDTOF0_DEL           1.006                  3.566  2
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[128]
                                                                                   NET DELAY             0.312                  3.878  2
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/i392_4_lut_4_lut/C->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/i392_4_lut_4_lut/Z
                                              SLICE_R54C111D                       CTOF_DEL              0.213                  4.091  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_valid_N_13318
                                                                                   NET DELAY             0.000                  4.091  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_valid_c.ff_inst/DF
                                                                                   ENDPOINT              0.000                  4.091  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_valid_c.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11550/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.412,
            "delay":0.320
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.702,
            "delay":0.290
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.702,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-1.988,
            "delay":-2.691
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.412,
            "delay":0.576
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.412,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-1.204,
            "delay":0.208
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.835,
            "delay":0.369
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.261,
            "delay":2.097
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.261,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
                                                                                   CONSTRAINT            0.000                  0.092  1
    pll_refclk_i                              eval_top                             CLOCK LATENCY         0.000                  0.092  1
    pll_refclk_i                                                                   NET DELAY             0.000                  0.092  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL              0.320                  0.412  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY             0.290                  0.702  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                           0.000                  0.702  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                          -2.691                 -1.988  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY             0.576                 -1.412  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL           0.000                 -1.412  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY             0.208                 -1.204  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL         0.369                 -0.835  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY             2.097                  1.261  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_valid_c.ff_inst/CLK
                                                                                   CLOCK PIN             0.000                  1.261  1
                                                                                   Uncertainty        -(0.000)                  1.261
                                                                                   Common Path Skew      0.000                  1.261
                                                                                   Setup time        -(-0.058)                  1.319
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Required Time                                                                                                               1.319
    Arrival Time                                                                                                             -(4.090)
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Path Slack  (Failed)                                                                                                       -2.771

    ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.ramw_inst/WDO0  (SLICE_R49C112C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_req_valid_c.ff_inst/DF  (SLICE_R50C112D)
    Source Clock     : clk_w (R)
    Destination Clock: sclk_o (R)
    Logic Level      : 3
    Delay Ratio      : 18.2% (route), 81.8% (logic)
    Clock Skew       : -1.391 ns
    Setup Constraint : 0.092 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -2.731 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_ctrl_fifo.u_fifo_dc.wr_addr_r_0__I_0.SLICE_2841/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":2.559,
            "delay":2.559
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":2.559,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.169,
            "delay":-2.390
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.560,
            "delay":2.391
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.560,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY         0.000                  0.000  2
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY             2.559                  2.559  2
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                           0.000                  2.559  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                          -2.390                  0.169  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY             2.391                  2.560  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.ramw_inst/WCK
                                                                                   CLOCK PIN             0.000                  2.560  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.ramw_inst/WDO0",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_ctrl_fifo.u_fifo_dc.wr_addr_r_0__I_0.SLICE_2841/WDO0"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_req_valid_c.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11549/DI0"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_ctrl_fifo.u_fifo_dc.wr_addr_r_0__I_0.SLICE_2841/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.ramw_inst/WDO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_ctrl_fifo.u_fifo_dc.wr_addr_r_0__I_0.SLICE_2841/WDO0"
            },
            "arrive":2.560,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.wdo0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_ctrl_fifo.u_fifo_dc.wr_addr_r_0__I_0.wdo0"
            },
            "arrive":2.560,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.dpram_inst_0/DI0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_ctrl_fifo.u_fifo_dc.SLICE_2842/WDI0"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.dpram_inst_0/DO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_ctrl_fifo.u_fifo_dc.SLICE_2842/F0"
            },
            "arrive":3.566,
            "delay":1.006
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/out_raw[0]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_ctrl_fifo.u_fifo_dc.out_raw[0]"
            },
            "arrive":3.838,
            "delay":0.272
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_ctrl_fifo_rd_I_0_2_4_lut_4_lut/C",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11549/C0"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_ctrl_fifo_rd_I_0_2_4_lut_4_lut/Z",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11549/F0"
            },
            "arrive":4.051,
            "delay":0.213
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_req_valid_nxt",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.wr_req_valid_nxt"
            },
            "arrive":4.051,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":4.051,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.ramw_inst/WDO0
                                              SLICE_R49C112C                       CLKTOQWD_DEL          0.000                  2.560  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.wdo0
                                                                                   NET DELAY             0.000                  2.560  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.dpram_inst_0/DI0->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.dpram_inst_0/DO0
                                              SLICE_R49C112A                       QWDTOF0_DEL           1.006                  3.566  2
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/out_raw[0]
                                                                                   NET DELAY             0.272                  3.838  2
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_ctrl_fifo_rd_I_0_2_4_lut_4_lut/C->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_ctrl_fifo_rd_I_0_2_4_lut_4_lut/Z
                                              SLICE_R50C112D                       CTOF_DEL              0.213                  4.051  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_req_valid_nxt
                                                                                   NET DELAY             0.000                  4.051  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_req_valid_c.ff_inst/DF
                                                                                   ENDPOINT              0.000                  4.051  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_req_valid_c.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11549/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.412,
            "delay":0.320
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.702,
            "delay":0.290
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.702,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-1.988,
            "delay":-2.691
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.412,
            "delay":0.576
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.412,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-1.204,
            "delay":0.208
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.835,
            "delay":0.369
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.261,
            "delay":2.097
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.261,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
                                                                                   CONSTRAINT            0.000                  0.092  1
    pll_refclk_i                              eval_top                             CLOCK LATENCY         0.000                  0.092  1
    pll_refclk_i                                                                   NET DELAY             0.000                  0.092  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL              0.320                  0.412  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY             0.290                  0.702  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                           0.000                  0.702  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                          -2.691                 -1.988  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY             0.576                 -1.412  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL           0.000                 -1.412  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY             0.208                 -1.204  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL         0.369                 -0.835  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY             2.097                  1.261  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_req_valid_c.ff_inst/CLK
                                                                                   CLOCK PIN             0.000                  1.261  1
                                                                                   Uncertainty        -(0.000)                  1.261
                                                                                   Common Path Skew      0.000                  1.261
                                                                                   Setup time        -(-0.058)                  1.319
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Required Time                                                                                                               1.319
    Arrival Time                                                                                                             -(4.050)
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Path Slack  (Failed)                                                                                                       -2.731

    ++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WDO1  (SLICE_R56C111C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_data_last.ff_inst/DF  (SLICE_R54C111C)
    Source Clock     : clk_w (R)
    Destination Clock: sclk_o (R)
    Logic Level      : 3
    Delay Ratio      : 18.0% (route), 82.0% (logic)
    Clock Skew       : -1.391 ns
    Setup Constraint : 0.092 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -2.727 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_8.SLICE_2787/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":2.559,
            "delay":2.559
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":2.559,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.169,
            "delay":-2.390
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.560,
            "delay":2.391
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.560,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY         0.000                  0.000  2
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY             2.559                  2.559  2
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                           0.000                  2.559  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                          -2.390                  0.169  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY             2.391                  2.560  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WCK
                                                                                   CLOCK PIN             0.000                  2.560  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WDO1",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_8.SLICE_2787/WDO1"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_data_last.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11551/DI0"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_8.SLICE_2787/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WDO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_8.SLICE_2787/WDO1"
            },
            "arrive":2.560,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.wdo1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_8.wdo1"
            },
            "arrive":2.560,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.dpram_inst_0/DI1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2788/WDI1"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.dpram_inst_0/DO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2788/F1"
            },
            "arrive":3.566,
            "delay":1.006
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[129]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.out_raw[129]"
            },
            "arrive":3.834,
            "delay":0.268
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/i393_4_lut_4_lut/C",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11551/D0"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/i393_4_lut_4_lut/Z",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11551/F0"
            },
            "arrive":4.047,
            "delay":0.213
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_last_N_13317",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.wr_last_N_13317"
            },
            "arrive":4.047,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":4.047,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WDO1
                                              SLICE_R56C111C                       CLKTOQWD_DEL          0.000                  2.560  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.wdo1
                                                                                   NET DELAY             0.000                  2.560  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.dpram_inst_0/DI1->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.dpram_inst_0/DO1
                                              SLICE_R56C111A                       QWDTOF1_DEL           1.006                  3.566  2
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[129]
                                                                                   NET DELAY             0.268                  3.834  2
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/i393_4_lut_4_lut/C->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/i393_4_lut_4_lut/Z
                                              SLICE_R54C111C                       CTOF_DEL              0.213                  4.047  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_last_N_13317
                                                                                   NET DELAY             0.000                  4.047  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_data_last.ff_inst/DF
                                                                                   ENDPOINT              0.000                  4.047  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_data_last.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11551/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.412,
            "delay":0.320
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.702,
            "delay":0.290
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.702,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-1.988,
            "delay":-2.691
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.412,
            "delay":0.576
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.412,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-1.204,
            "delay":0.208
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.835,
            "delay":0.369
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.261,
            "delay":2.097
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.261,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
                                                                                   CONSTRAINT            0.000                  0.092  1
    pll_refclk_i                              eval_top                             CLOCK LATENCY         0.000                  0.092  1
    pll_refclk_i                                                                   NET DELAY             0.000                  0.092  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL              0.320                  0.412  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY             0.290                  0.702  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                           0.000                  0.702  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                          -2.691                 -1.988  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY             0.576                 -1.412  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL           0.000                 -1.412  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY             0.208                 -1.204  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL         0.369                 -0.835  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY             2.097                  1.261  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_data_last.ff_inst/CLK
                                                                                   CLOCK PIN             0.000                  1.261  1
                                                                                   Uncertainty        -(0.000)                  1.261
                                                                                   Common Path Skew      0.000                  1.261
                                                                                   Setup time        -(-0.058)                  1.319
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Required Time                                                                                                               1.319
    Arrival Time                                                                                                             -(4.046)
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Path Slack  (Failed)                                                                                                       -2.727

    ++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.ramw_inst/WDO1  (SLICE_R63C118C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i42.ff_inst/DF  (SLICE_R63C118A)
    Source Clock     : clk_w (R)
    Destination Clock: sclk_o (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : -1.391 ns
    Setup Constraint : 0.092 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -2.247 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_30.SLICE_2727/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":2.559,
            "delay":2.559
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":2.559,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.169,
            "delay":-2.390
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.560,
            "delay":2.391
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.560,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY         0.000                  0.000  2
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY             2.559                  2.559  2
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                           0.000                  2.559  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                          -2.390                  0.169  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY             2.391                  2.560  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.ramw_inst/WCK
                                                                                   CLOCK PIN             0.000                  2.560  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.ramw_inst/WDO1",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_30.SLICE_2727/WDO1"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i42.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2728/DI1"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_30.SLICE_2727/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.ramw_inst/WDO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_30.SLICE_2727/WDO1"
            },
            "arrive":2.560,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.wdo1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_30.wdo1"
            },
            "arrive":2.560,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.dpram_inst_0/DI1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2728/WDI1"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.dpram_inst_0/DO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2728/F1"
            },
            "arrive":3.566,
            "delay":1.006
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[41]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.out_raw[41]"
            },
            "arrive":3.566,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":3.566,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.ramw_inst/WDO1
                                              SLICE_R63C118C                       CLKTOQWD_DEL          0.000                  2.560  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.wdo1
                                                                                   NET DELAY             0.000                  2.560  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.dpram_inst_0/DI1->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.dpram_inst_0/DO1
                                              SLICE_R63C118A                       QWDTOF1_DEL           1.006                  3.566  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[41]
                                                                                   NET DELAY             0.000                  3.566  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i42.ff_inst/DF
                                                                                   ENDPOINT              0.000                  3.566  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i41.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2728/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.412,
            "delay":0.320
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.702,
            "delay":0.290
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.702,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-1.988,
            "delay":-2.691
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.412,
            "delay":0.576
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.412,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-1.204,
            "delay":0.208
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.835,
            "delay":0.369
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.261,
            "delay":2.097
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.261,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
                                                                                   CONSTRAINT            0.000                  0.092  1
    pll_refclk_i                              eval_top                             CLOCK LATENCY         0.000                  0.092  1
    pll_refclk_i                                                                   NET DELAY             0.000                  0.092  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL              0.320                  0.412  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY             0.290                  0.702  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                           0.000                  0.702  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                          -2.691                 -1.988  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY             0.576                 -1.412  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL           0.000                 -1.412  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY             0.208                 -1.204  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL         0.369                 -0.835  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY             2.097                  1.261  6014
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i41.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i42.ff_inst/CLK}
                                                                                   CLOCK PIN             0.000                  1.261  1
                                                                                   Uncertainty        -(0.000)                  1.261
                                                                                   Common Path Skew      0.000                  1.261
                                                                                   Setup time        -(-0.057)                  1.318
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Required Time                                                                                                               1.318
    Arrival Time                                                                                                             -(3.565)
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Path Slack  (Failed)                                                                                                       -2.247

    ++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WDO3  (SLICE_R58C118C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i84.ff_inst/DF  (SLICE_R58C118B)
    Source Clock     : clk_w (R)
    Destination Clock: sclk_o (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : -1.391 ns
    Setup Constraint : 0.092 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -2.247 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_20.SLICE_2724/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":2.559,
            "delay":2.559
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":2.559,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.169,
            "delay":-2.390
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.560,
            "delay":2.391
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.560,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY         0.000                  0.000  2
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY             2.559                  2.559  2
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                           0.000                  2.559  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                          -2.390                  0.169  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY             2.391                  2.560  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WCK
                                                                                   CLOCK PIN             0.000                  2.560  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WDO3",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_20.SLICE_2724/WDO3"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i84.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2726/DI1"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_20.SLICE_2724/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WDO3",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_20.SLICE_2724/WDO3"
            },
            "arrive":2.560,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.wdo3",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_20.wdo3"
            },
            "arrive":2.560,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.dpram_inst_1/DI1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2726/WDI1"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.dpram_inst_1/DO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2726/F1"
            },
            "arrive":3.566,
            "delay":1.006
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[83]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.out_raw[83]"
            },
            "arrive":3.566,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":3.566,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WDO3
                                              SLICE_R58C118C                       CLKTOQWD_DEL          0.000                  2.560  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.wdo3
                                                                                   NET DELAY             0.000                  2.560  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.dpram_inst_1/DI1->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.dpram_inst_1/DO1
                                              SLICE_R58C118B                       QWDTOF1_DEL           1.006                  3.566  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[83]
                                                                                   NET DELAY             0.000                  3.566  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i84.ff_inst/DF
                                                                                   ENDPOINT              0.000                  3.566  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i83.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2726/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.412,
            "delay":0.320
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.702,
            "delay":0.290
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.702,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-1.988,
            "delay":-2.691
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.412,
            "delay":0.576
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.412,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-1.204,
            "delay":0.208
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.835,
            "delay":0.369
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.261,
            "delay":2.097
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.261,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
                                                                                   CONSTRAINT            0.000                  0.092  1
    pll_refclk_i                              eval_top                             CLOCK LATENCY         0.000                  0.092  1
    pll_refclk_i                                                                   NET DELAY             0.000                  0.092  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL              0.320                  0.412  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY             0.290                  0.702  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                           0.000                  0.702  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                          -2.691                 -1.988  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY             0.576                 -1.412  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL           0.000                 -1.412  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY             0.208                 -1.204  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL         0.369                 -0.835  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY             2.097                  1.261  6014
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i83.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i84.ff_inst/CLK}
                                                                                   CLOCK PIN             0.000                  1.261  1
                                                                                   Uncertainty        -(0.000)                  1.261
                                                                                   Common Path Skew      0.000                  1.261
                                                                                   Setup time        -(-0.057)                  1.318
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Required Time                                                                                                               1.318
    Arrival Time                                                                                                             -(3.565)
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Path Slack  (Failed)                                                                                                       -2.247

    ++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WDO1  (SLICE_R58C118C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i82.ff_inst/DF  (SLICE_R58C118A)
    Source Clock     : clk_w (R)
    Destination Clock: sclk_o (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : -1.391 ns
    Setup Constraint : 0.092 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -2.247 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_20.SLICE_2724/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":2.559,
            "delay":2.559
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":2.559,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.169,
            "delay":-2.390
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.560,
            "delay":2.391
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.560,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY         0.000                  0.000  2
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY             2.559                  2.559  2
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                           0.000                  2.559  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                          -2.390                  0.169  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY             2.391                  2.560  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WCK
                                                                                   CLOCK PIN             0.000                  2.560  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WDO1",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_20.SLICE_2724/WDO1"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i82.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2725/DI1"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_20.SLICE_2724/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WDO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_20.SLICE_2724/WDO1"
            },
            "arrive":2.560,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.wdo1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_20.wdo1"
            },
            "arrive":2.560,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.dpram_inst_0/DI1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2725/WDI1"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.dpram_inst_0/DO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2725/F1"
            },
            "arrive":3.566,
            "delay":1.006
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[81]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.out_raw[81]"
            },
            "arrive":3.566,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":3.566,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WDO1
                                              SLICE_R58C118C                       CLKTOQWD_DEL          0.000                  2.560  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.wdo1
                                                                                   NET DELAY             0.000                  2.560  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.dpram_inst_0/DI1->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.dpram_inst_0/DO1
                                              SLICE_R58C118A                       QWDTOF1_DEL           1.006                  3.566  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[81]
                                                                                   NET DELAY             0.000                  3.566  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i82.ff_inst/DF
                                                                                   ENDPOINT              0.000                  3.566  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i81.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2725/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.412,
            "delay":0.320
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.702,
            "delay":0.290
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.702,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-1.988,
            "delay":-2.691
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.412,
            "delay":0.576
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.412,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-1.204,
            "delay":0.208
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.835,
            "delay":0.369
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.261,
            "delay":2.097
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.261,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
                                                                                   CONSTRAINT            0.000                  0.092  1
    pll_refclk_i                              eval_top                             CLOCK LATENCY         0.000                  0.092  1
    pll_refclk_i                                                                   NET DELAY             0.000                  0.092  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL              0.320                  0.412  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY             0.290                  0.702  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                           0.000                  0.702  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                          -2.691                 -1.988  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY             0.576                 -1.412  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL           0.000                 -1.412  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY             0.208                 -1.204  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL         0.369                 -0.835  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY             2.097                  1.261  6014
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i81.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i82.ff_inst/CLK}
                                                                                   CLOCK PIN             0.000                  1.261  1
                                                                                   Uncertainty        -(0.000)                  1.261
                                                                                   Common Path Skew      0.000                  1.261
                                                                                   Setup time        -(-0.057)                  1.318
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Required Time                                                                                                               1.318
    Arrival Time                                                                                                             -(3.565)
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Path Slack  (Failed)                                                                                                       -2.247

    ++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WDO3  (SLICE_R63C116C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i48.ff_inst/DF  (SLICE_R63C116B)
    Source Clock     : clk_w (R)
    Destination Clock: sclk_o (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : -1.391 ns
    Setup Constraint : 0.092 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -2.247 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_29.SLICE_2721/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":2.559,
            "delay":2.559
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":2.559,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.169,
            "delay":-2.390
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.560,
            "delay":2.391
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.560,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY         0.000                  0.000  2
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY             2.559                  2.559  2
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                           0.000                  2.559  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                          -2.390                  0.169  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY             2.391                  2.560  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WCK
                                                                                   CLOCK PIN             0.000                  2.560  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WDO3",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_29.SLICE_2721/WDO3"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i48.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2723/DI1"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_29.SLICE_2721/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WDO3",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_29.SLICE_2721/WDO3"
            },
            "arrive":2.560,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.wdo3",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_29.wdo3"
            },
            "arrive":2.560,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.dpram_inst_1/DI1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2723/WDI1"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.dpram_inst_1/DO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2723/F1"
            },
            "arrive":3.566,
            "delay":1.006
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[47]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.out_raw[47]"
            },
            "arrive":3.566,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":3.566,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WDO3
                                              SLICE_R63C116C                       CLKTOQWD_DEL          0.000                  2.560  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.wdo3
                                                                                   NET DELAY             0.000                  2.560  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.dpram_inst_1/DI1->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.dpram_inst_1/DO1
                                              SLICE_R63C116B                       QWDTOF1_DEL           1.006                  3.566  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[47]
                                                                                   NET DELAY             0.000                  3.566  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i48.ff_inst/DF
                                                                                   ENDPOINT              0.000                  3.566  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i47.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2723/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.412,
            "delay":0.320
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.702,
            "delay":0.290
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.702,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-1.988,
            "delay":-2.691
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.412,
            "delay":0.576
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.412,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-1.204,
            "delay":0.208
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.835,
            "delay":0.369
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.261,
            "delay":2.097
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.261,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
                                                                                   CONSTRAINT            0.000                  0.092  1
    pll_refclk_i                              eval_top                             CLOCK LATENCY         0.000                  0.092  1
    pll_refclk_i                                                                   NET DELAY             0.000                  0.092  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL              0.320                  0.412  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY             0.290                  0.702  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                           0.000                  0.702  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                          -2.691                 -1.988  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY             0.576                 -1.412  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL           0.000                 -1.412  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY             0.208                 -1.204  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL         0.369                 -0.835  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY             2.097                  1.261  6014
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i47.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i48.ff_inst/CLK}
                                                                                   CLOCK PIN             0.000                  1.261  1
                                                                                   Uncertainty        -(0.000)                  1.261
                                                                                   Common Path Skew      0.000                  1.261
                                                                                   Setup time        -(-0.057)                  1.318
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Required Time                                                                                                               1.318
    Arrival Time                                                                                                             -(3.565)
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Path Slack  (Failed)                                                                                                       -2.247

    ++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WDO1  (SLICE_R63C116C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i46.ff_inst/DF  (SLICE_R63C116A)
    Source Clock     : clk_w (R)
    Destination Clock: sclk_o (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : -1.391 ns
    Setup Constraint : 0.092 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -2.247 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_29.SLICE_2721/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":2.559,
            "delay":2.559
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":2.559,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.169,
            "delay":-2.390
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.560,
            "delay":2.391
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.560,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY         0.000                  0.000  2
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY             2.559                  2.559  2
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                           0.000                  2.559  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                          -2.390                  0.169  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY             2.391                  2.560  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WCK
                                                                                   CLOCK PIN             0.000                  2.560  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WDO1",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_29.SLICE_2721/WDO1"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i46.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2722/DI1"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_29.SLICE_2721/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WDO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_29.SLICE_2721/WDO1"
            },
            "arrive":2.560,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.wdo1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_29.wdo1"
            },
            "arrive":2.560,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.dpram_inst_0/DI1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2722/WDI1"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.dpram_inst_0/DO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2722/F1"
            },
            "arrive":3.566,
            "delay":1.006
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[45]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.out_raw[45]"
            },
            "arrive":3.566,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":3.566,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WDO1
                                              SLICE_R63C116C                       CLKTOQWD_DEL          0.000                  2.560  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.wdo1
                                                                                   NET DELAY             0.000                  2.560  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.dpram_inst_0/DI1->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.dpram_inst_0/DO1
                                              SLICE_R63C116A                       QWDTOF1_DEL           1.006                  3.566  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[45]
                                                                                   NET DELAY             0.000                  3.566  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i46.ff_inst/DF
                                                                                   ENDPOINT              0.000                  3.566  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i45.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2722/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.412,
            "delay":0.320
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.702,
            "delay":0.290
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.702,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-1.988,
            "delay":-2.691
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.412,
            "delay":0.576
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.412,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-1.204,
            "delay":0.208
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.835,
            "delay":0.369
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.261,
            "delay":2.097
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.261,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
                                                                                   CONSTRAINT            0.000                  0.092  1
    pll_refclk_i                              eval_top                             CLOCK LATENCY         0.000                  0.092  1
    pll_refclk_i                                                                   NET DELAY             0.000                  0.092  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL              0.320                  0.412  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY             0.290                  0.702  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                           0.000                  0.702  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                          -2.691                 -1.988  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY             0.576                 -1.412  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL           0.000                 -1.412  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY             0.208                 -1.204  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL         0.369                 -0.835  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY             2.097                  1.261  6014
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i45.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i46.ff_inst/CLK}
                                                                                   CLOCK PIN             0.000                  1.261  1
                                                                                   Uncertainty        -(0.000)                  1.261
                                                                                   Common Path Skew      0.000                  1.261
                                                                                   Setup time        -(-0.057)                  1.318
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Required Time                                                                                                               1.318
    Arrival Time                                                                                                             -(3.565)
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Path Slack  (Failed)                                                                                                       -2.247

    ++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WDO3  (SLICE_R60C111C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i56.ff_inst/DF  (SLICE_R60C111B)
    Source Clock     : clk_w (R)
    Destination Clock: sclk_o (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : -1.391 ns
    Setup Constraint : 0.092 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -2.247 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_27.SLICE_2718/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":2.559,
            "delay":2.559
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":2.559,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.169,
            "delay":-2.390
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.560,
            "delay":2.391
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.560,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY         0.000                  0.000  2
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY             2.559                  2.559  2
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                           0.000                  2.559  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                          -2.390                  0.169  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY             2.391                  2.560  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WCK
                                                                                   CLOCK PIN             0.000                  2.560  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WDO3",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_27.SLICE_2718/WDO3"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i56.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2720/DI1"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_27.SLICE_2718/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WDO3",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_27.SLICE_2718/WDO3"
            },
            "arrive":2.560,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.wdo3",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_27.wdo3"
            },
            "arrive":2.560,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.dpram_inst_1/DI1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2720/WDI1"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.dpram_inst_1/DO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2720/F1"
            },
            "arrive":3.566,
            "delay":1.006
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[55]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.out_raw[55]"
            },
            "arrive":3.566,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":3.566,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WDO3
                                              SLICE_R60C111C                       CLKTOQWD_DEL          0.000                  2.560  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.wdo3
                                                                                   NET DELAY             0.000                  2.560  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.dpram_inst_1/DI1->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.dpram_inst_1/DO1
                                              SLICE_R60C111B                       QWDTOF1_DEL           1.006                  3.566  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[55]
                                                                                   NET DELAY             0.000                  3.566  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i56.ff_inst/DF
                                                                                   ENDPOINT              0.000                  3.566  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i55.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2720/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.412,
            "delay":0.320
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.702,
            "delay":0.290
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.702,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-1.988,
            "delay":-2.691
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.412,
            "delay":0.576
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.412,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-1.204,
            "delay":0.208
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.835,
            "delay":0.369
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.261,
            "delay":2.097
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.261,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
                                                                                   CONSTRAINT            0.000                  0.092  1
    pll_refclk_i                              eval_top                             CLOCK LATENCY         0.000                  0.092  1
    pll_refclk_i                                                                   NET DELAY             0.000                  0.092  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL              0.320                  0.412  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY             0.290                  0.702  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                           0.000                  0.702  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                          -2.691                 -1.988  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY             0.576                 -1.412  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL           0.000                 -1.412  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY             0.208                 -1.204  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL         0.369                 -0.835  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY             2.097                  1.261  6014
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i55.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i56.ff_inst/CLK}
                                                                                   CLOCK PIN             0.000                  1.261  1
                                                                                   Uncertainty        -(0.000)                  1.261
                                                                                   Common Path Skew      0.000                  1.261
                                                                                   Setup time        -(-0.057)                  1.318
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Required Time                                                                                                               1.318
    Arrival Time                                                                                                             -(3.565)
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Path Slack  (Failed)                                                                                                       -2.247

    ++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WDO1  (SLICE_R60C111C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i54.ff_inst/DF  (SLICE_R60C111A)
    Source Clock     : clk_w (R)
    Destination Clock: sclk_o (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : -1.391 ns
    Setup Constraint : 0.092 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -2.247 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_27.SLICE_2718/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":2.559,
            "delay":2.559
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":2.559,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.169,
            "delay":-2.390
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.560,
            "delay":2.391
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.560,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY         0.000                  0.000  2
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY             2.559                  2.559  2
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                           0.000                  2.559  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                          -2.390                  0.169  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY             2.391                  2.560  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WCK
                                                                                   CLOCK PIN             0.000                  2.560  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WDO1",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_27.SLICE_2718/WDO1"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i54.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2719/DI1"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_27.SLICE_2718/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WDO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_27.SLICE_2718/WDO1"
            },
            "arrive":2.560,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.wdo1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_27.wdo1"
            },
            "arrive":2.560,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.dpram_inst_0/DI1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2719/WDI1"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.dpram_inst_0/DO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2719/F1"
            },
            "arrive":3.566,
            "delay":1.006
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[53]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.out_raw[53]"
            },
            "arrive":3.566,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":3.566,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WDO1
                                              SLICE_R60C111C                       CLKTOQWD_DEL          0.000                  2.560  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.wdo1
                                                                                   NET DELAY             0.000                  2.560  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.dpram_inst_0/DI1->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.dpram_inst_0/DO1
                                              SLICE_R60C111A                       QWDTOF1_DEL           1.006                  3.566  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[53]
                                                                                   NET DELAY             0.000                  3.566  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i54.ff_inst/DF
                                                                                   ENDPOINT              0.000                  3.566  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i53.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2719/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.412,
            "delay":0.320
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.702,
            "delay":0.290
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.702,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-1.988,
            "delay":-2.691
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.412,
            "delay":0.576
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.412,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-1.204,
            "delay":0.208
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.835,
            "delay":0.369
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.261,
            "delay":2.097
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.261,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
                                                                                   CONSTRAINT            0.000                  0.092  1
    pll_refclk_i                              eval_top                             CLOCK LATENCY         0.000                  0.092  1
    pll_refclk_i                                                                   NET DELAY             0.000                  0.092  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL              0.320                  0.412  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY             0.290                  0.702  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                           0.000                  0.702  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                          -2.691                 -1.988  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY             0.576                 -1.412  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL           0.000                 -1.412  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY             0.208                 -1.204  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL         0.369                 -0.835  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY             2.097                  1.261  6014
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i53.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i54.ff_inst/CLK}
                                                                                   CLOCK PIN             0.000                  1.261  1
                                                                                   Uncertainty        -(0.000)                  1.261
                                                                                   Common Path Skew      0.000                  1.261
                                                                                   Setup time        -(-0.057)                  1.318
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Required Time                                                                                                               1.318
    Arrival Time                                                                                                             -(3.565)
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Path Slack  (Failed)                                                                                                       -2.247

    +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
                        End of Detailed Report for timing paths
    +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    ##########################################################

    3  Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees
    3.1  Clock Summary
    3.1.1 Clock "sclk_o"

    create_generated_clock -name {sclk_o} -source [get_pins {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN}] -divide_by 4 [get_pins {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT }]

    Single Clock Domain
    -------------------------------------------------------------------------------------------------------
                  Clock sclk_o              |                    |       Period       |     Frequency
    -------------------------------------------------------------------------------------------------------
     From sclk_o                            |             Target |           7.500 ns |        133.333 MHz
                                            | Actual (all paths) |           6.568 ns |        152.253 MHz
    u_mem/lscc_lpddr4_mc_inst/u_ctrl_wrap/u_controller/secured_instance_272_1/secured_instance_209_1/secured_instance_208_142/secured_instance_207_0/secured_instance_206_0/secured_instance_205_0/secured_instance_204_0/CLKW (MPW)
                                            |   (50% duty cycle) |           2.942 ns |        339.905 MHz
    -------------------------------------------------------------------------------------------------------

    Clock Domain Crossing
    ------------------------------------------------------------------------------------------------------
                  Clock sclk_o              |   Worst Time Between Edges   |           Comment
    ------------------------------------------------------------------------------------------------------
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w
                                            |                         ---- |                      No path
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w
                                            |                     1.875 ns |             slack = 3.741 ns
     From clk_w                             |                     0.092 ns |            slack = -2.882 ns
     From out_clk1_c                        |                         ---- |                      No path
     From osc_clk_90                        |                         ---- |                      No path
     From pll_refclk_i                      |                         ---- |                      No path
    ------------------------------------------------------------------------------------------------------
    3.1.2 Clock "u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w"

    create_generated_clock -name {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w} -source [get_pins {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -divide_by 1 [get_pins {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP }]

    Single Clock Domain
    ---------------------------------------------------------------------------------------------------------------------
    Clock u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w|                    |       Period       |     Frequency
    ---------------------------------------------------------------------------------------------------------------------
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w|             Target |          10.000 ns |        100.000 MHz
                                                          | Actual (all paths) |               ---- |               ----
    ---------------------------------------------------------------------------------------------------------------------

    Clock Domain Crossing
    --------------------------------------------------------------------------------------------------------------------
    Clock u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w|   Worst Time Between Edges   |           Comment
    --------------------------------------------------------------------------------------------------------------------
     From sclk_o                                          |                         ---- |                      No path
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w       |                         ---- |                      No path
     From clk_w                                           |                         ---- |                      No path
     From out_clk1_c                                      |                         ---- |                      No path
     From osc_clk_90                                      |                         ---- |                      No path
     From pll_refclk_i                                    |                         ---- |                      No path
    --------------------------------------------------------------------------------------------------------------------
    3.1.3 Clock "u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w"

    create_generated_clock -name {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w} -source [get_pins {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 16 -divide_by 3 [get_pins {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS }]

    Single Clock Domain
    --------------------------------------------------------------------------------------------------------------
    Clock u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w|                    |       Period       |     Frequency
    --------------------------------------------------------------------------------------------------------------
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w|             Target |           1.875 ns |        533.333 MHz
                                                   | Actual (all paths) |           1.874 ns |        533.618 MHz
    {u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/DQS[0].DQS_X4.u_ODDRX4DQS/WRCLK   u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/TS[0].TS_X4.u_TSHX4DQS/WRCLK} (MPW)
                                                   |   (50% duty cycle) |           1.874 ns |        533.618 MHz
    --------------------------------------------------------------------------------------------------------------

    Clock Domain Crossing
    -------------------------------------------------------------------------------------------------------------
    Clock u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w|   Worst Time Between Edges   |           Comment
    -------------------------------------------------------------------------------------------------------------
     From sclk_o                                   |                     1.875 ns |             slack = 2.669 ns
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w
                                                   |                         ---- |                      No path
     From clk_w                                    |                         ---- |                      No path
     From out_clk1_c                               |                         ---- |                      No path
     From osc_clk_90                               |                         ---- |                      No path
     From pll_refclk_i                             |                         ---- |                      No path
    -------------------------------------------------------------------------------------------------------------
    3.1.4 Clock "clk_w"

    create_generated_clock -name {clk_w} -source [get_pins {ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 3 -divide_by 2 [get_pins {ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP }]

    Single Clock Domain
    -------------------------------------------------------------------------------------------------------
                  Clock clk_w               |                    |       Period       |     Frequency
    -------------------------------------------------------------------------------------------------------
     From clk_w                             |             Target |           7.407 ns |        135.000 MHz
                                            | Actual (all paths) |           7.214 ns |        138.619 MHz
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_lpddr4_mc_rd_rtrn_ebr_inst/lscc_ram_dp_inst/mem_main/NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[3].no_init.u_mem0/LIFCL_MEM.pdp16k.PDP16K_MODE_inst/CLKR (MPW)
                                            |   (50% duty cycle) |           2.942 ns |        339.905 MHz
    -------------------------------------------------------------------------------------------------------

    Clock Domain Crossing
    ------------------------------------------------------------------------------------------------------
                  Clock clk_w               |   Worst Time Between Edges   |           Comment
    ------------------------------------------------------------------------------------------------------
     From sclk_o                            |                     0.092 ns |            slack = -0.305 ns
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w
                                            |                         ---- |                      No path
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w
                                            |                         ---- |                      No path
     From out_clk1_c                        |                         ---- |                      No path
     From osc_clk_90                        |                         ---- |                      No path
     From pll_refclk_i                      |                         ---- |                      No path
    ------------------------------------------------------------------------------------------------------
    3.1.5 Clock "out_clk1_c"

    create_generated_clock -name {out_clk1_c} -source [get_pins {ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -divide_by 1 [get_pins {ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS }]

    Single Clock Domain
    -------------------------------------------------------------------------------------------------------
                Clock out_clk1_c            |                    |       Period       |     Frequency
    -------------------------------------------------------------------------------------------------------
     From out_clk1_c                        |             Target |          11.111 ns |         90.000 MHz
                                            | Actual (all paths) |          10.355 ns |         96.572 MHz
    out_clk1_pad.bb_inst/B (MPW)            |   (50% duty cycle) |           5.000 ns |        200.000 MHz
    -------------------------------------------------------------------------------------------------------

    Clock Domain Crossing
    ------------------------------------------------------------------------------------------------------
                Clock out_clk1_c            |   Worst Time Between Edges   |           Comment
    ------------------------------------------------------------------------------------------------------
     From sclk_o                            |                         ---- |                      No path
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w
                                            |                         ---- |                      No path
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w
                                            |                         ---- |                      No path
     From clk_w                             |                         ---- |                      No path
     From osc_clk_90                        |                         ---- |                      No path
     From pll_refclk_i                      |                         ---- |                      No path
    ------------------------------------------------------------------------------------------------------
    3.1.6 Clock "osc_clk_90"

    create_clock -name {osc_clk_90} -period 11.1111 [get_pins {osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT }]

    Single Clock Domain
    -------------------------------------------------------------------------------------------------------
                Clock osc_clk_90            |                    |       Period       |     Frequency
    -------------------------------------------------------------------------------------------------------
     From osc_clk_90                        |             Target |          11.111 ns |         90.000 MHz
                                            | Actual (all paths) |           4.354 ns |        229.674 MHz
    osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT (MPW)
                                            |   (50% duty cycle) |           4.354 ns |        229.674 MHz
    -------------------------------------------------------------------------------------------------------

    Clock Domain Crossing
    ------------------------------------------------------------------------------------------------------
                Clock osc_clk_90            |   Worst Time Between Edges   |           Comment
    ------------------------------------------------------------------------------------------------------
     From sclk_o                            |                         ---- |                      No path
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w
                                            |                         ---- |                      No path
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w
                                            |                         ---- |                      No path
     From clk_w                             |                         ---- |                      No path
     From out_clk1_c                        |                         ---- |                      No path
     From pll_refclk_i                      |                         ---- |                      No path
    ------------------------------------------------------------------------------------------------------
    3.1.7 Clock "pll_refclk_i"

    create_clock -name {pll_refclk_i} -period 10 [get_ports pll_refclk_i]

    Single Clock Domain
    -------------------------------------------------------------------------------------------------------
               Clock pll_refclk_i           |                    |       Period       |     Frequency
    -------------------------------------------------------------------------------------------------------
     From pll_refclk_i                      |             Target |          10.000 ns |        100.000 MHz
                                            | Actual (all paths) |           1.874 ns |        533.618 MHz
    pll_refclk_i_pad.bb_inst/B (MPW)        |   (50% duty cycle) |           1.874 ns |        533.618 MHz
    -------------------------------------------------------------------------------------------------------

    Clock Domain Crossing
    ------------------------------------------------------------------------------------------------------
               Clock pll_refclk_i           |   Worst Time Between Edges   |           Comment
    ------------------------------------------------------------------------------------------------------
     From sclk_o                            |                         ---- |                      No path
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/fbclk_w
                                            |                         ---- |                      No path
     From u_mem/lscc_lpddr4_mc_inst/u_lp4mem/eclk_w
                                            |                         ---- |                      No path
     From clk_w                             |                         ---- |                      No path
     From out_clk1_c                        |                         ---- |                      No path
     From osc_clk_90                        |                         ---- |                      No path
    ------------------------------------------------------------------------------------------------------

    3.2  Endpoint slacks
    -------------------------------------------------------
              Listing 10 End Points          |    Slack
    -------------------------------------------------------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_valid_c.ff_inst/DF
                                             |   -2.882 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_req_valid_c.ff_inst/DF
                                             |   -2.844 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_data_last.ff_inst/DF
                                             |   -2.838 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i42.ff_inst/DF
                                             |   -2.371 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i84.ff_inst/DF
                                             |   -2.371 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i82.ff_inst/DF
                                             |   -2.371 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i48.ff_inst/DF
                                             |   -2.371 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i46.ff_inst/DF
                                             |   -2.371 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i56.ff_inst/DF
                                             |   -2.371 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i54.ff_inst/DF
                                             |   -2.371 ns
    -------------------------------------------------------
                                             |
    Setup # of endpoints with negative slack:|         259
                                             |
    -------------------------------------------------------

    3.3  Detailed Report

    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Detail report of critical paths

    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

     +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
                        Detailed Report for timing paths
     +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

     ++++Path 1  ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WDO0  (SLICE_R56C111C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_valid_c.ff_inst/DF  (SLICE_R54C111D)
    Source Clock     : clk_w (R)
    Destination Clock: sclk_o (R)
    Logic Level      : 3
    Delay Ratio      : 19.6% (route), 80.4% (logic)
    Clock Skew       : -1.511 ns
    Setup Constraint : 0.092 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -2.882 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_8.SLICE_2787/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":2.736,
            "delay":2.736
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":2.736,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.179,
            "delay":-2.557
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.749,
            "delay":2.570
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.749,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY         0.000                  0.000  3
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY             2.736                  2.736  3
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                           0.000                  2.736  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                          -2.557                  0.179  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY             2.570                  2.749  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WCK
                                                                                   CLOCK PIN             0.000                  2.749  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WDO0",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_8.SLICE_2787/WDO0"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_valid_c.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11550/DI0"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_8.SLICE_2787/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WDO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_8.SLICE_2787/WDO0"
            },
            "arrive":2.749,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.wdo0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_8.wdo0"
            },
            "arrive":2.749,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.dpram_inst_0/DI0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2788/WDI0"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.dpram_inst_0/DO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2788/F0"
            },
            "arrive":3.759,
            "delay":1.010
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[128]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.out_raw[128]"
            },
            "arrive":4.058,
            "delay":0.299
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/i392_4_lut_4_lut/C",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11550/C0"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/i392_4_lut_4_lut/Z",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11550/F0"
            },
            "arrive":4.271,
            "delay":0.213
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_valid_N_13318",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.wr_valid_N_13318"
            },
            "arrive":4.271,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":4.271,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WDO0
                                              SLICE_R56C111C                       CLKTOQWD_DEL          0.000                  2.749  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.wdo0
                                                                                   NET DELAY             0.000                  2.749  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.dpram_inst_0/DI0->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.dpram_inst_0/DO0
                                              SLICE_R56C111A                       QWDTOF0_DEL           1.010                  3.759  2
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[128]
                                                                                   NET DELAY             0.299                  4.058  2
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/i392_4_lut_4_lut/C->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/i392_4_lut_4_lut/Z
                                              SLICE_R54C111D                       CTOF_DEL              0.213                  4.271  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_valid_N_13318
                                                                                   NET DELAY             0.000                  4.271  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_valid_c.ff_inst/DF
                                                                                   ENDPOINT              0.000                  4.271  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_valid_c.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11550/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.408,
            "delay":0.316
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.714,
            "delay":0.306
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.714,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-2.163,
            "delay":-2.878
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.543,
            "delay":0.620
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.543,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-1.319,
            "delay":0.224
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.922,
            "delay":0.397
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.330,
            "delay":2.253
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.330,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
                                                                                   CONSTRAINT            0.000                  0.092  1
    pll_refclk_i                              eval_top                             CLOCK LATENCY         0.000                  0.092  1
    pll_refclk_i                                                                   NET DELAY             0.000                  0.092  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL              0.316                  0.408  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY             0.306                  0.714  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                           0.000                  0.714  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                          -2.878                 -2.163  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY             0.620                 -1.543  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL           0.000                 -1.543  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY             0.224                 -1.319  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL         0.397                 -0.922  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY             2.253                  1.330  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_valid_c.ff_inst/CLK
                                                                                   CLOCK PIN             0.000                  1.330  1
                                                                                   Uncertainty        -(0.000)                  1.330
                                                                                   Common Path Skew      0.000                  1.330
                                                                                   Setup time        -(-0.058)                  1.388
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Required Time                                                                                                               1.388
    Arrival Time                                                                                                             -(4.270)
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Path Slack  (Failed)                                                                                                       -2.882

    ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.ramw_inst/WDO0  (SLICE_R49C112C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_req_valid_c.ff_inst/DF  (SLICE_R50C112D)
    Source Clock     : clk_w (R)
    Destination Clock: sclk_o (R)
    Logic Level      : 3
    Delay Ratio      : 17.6% (route), 82.4% (logic)
    Clock Skew       : -1.511 ns
    Setup Constraint : 0.092 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -2.844 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_ctrl_fifo.u_fifo_dc.wr_addr_r_0__I_0.SLICE_2841/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":2.736,
            "delay":2.736
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":2.736,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.179,
            "delay":-2.557
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.749,
            "delay":2.570
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.749,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY         0.000                  0.000  3
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY             2.736                  2.736  3
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                           0.000                  2.736  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                          -2.557                  0.179  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY             2.570                  2.749  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.ramw_inst/WCK
                                                                                   CLOCK PIN             0.000                  2.749  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.ramw_inst/WDO0",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_ctrl_fifo.u_fifo_dc.wr_addr_r_0__I_0.SLICE_2841/WDO0"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_req_valid_c.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11549/DI0"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_ctrl_fifo.u_fifo_dc.wr_addr_r_0__I_0.SLICE_2841/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.ramw_inst/WDO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_ctrl_fifo.u_fifo_dc.wr_addr_r_0__I_0.SLICE_2841/WDO0"
            },
            "arrive":2.749,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.wdo0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_ctrl_fifo.u_fifo_dc.wr_addr_r_0__I_0.wdo0"
            },
            "arrive":2.749,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.dpram_inst_0/DI0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_ctrl_fifo.u_fifo_dc.SLICE_2842/WDI0"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.dpram_inst_0/DO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_ctrl_fifo.u_fifo_dc.SLICE_2842/F0"
            },
            "arrive":3.759,
            "delay":1.010
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/out_raw[0]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_ctrl_fifo.u_fifo_dc.out_raw[0]"
            },
            "arrive":4.020,
            "delay":0.261
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_ctrl_fifo_rd_I_0_2_4_lut_4_lut/C",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11549/C0"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_ctrl_fifo_rd_I_0_2_4_lut_4_lut/Z",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11549/F0"
            },
            "arrive":4.233,
            "delay":0.213
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_req_valid_nxt",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.wr_req_valid_nxt"
            },
            "arrive":4.233,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":4.233,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.ramw_inst/WDO0
                                              SLICE_R49C112C                       CLKTOQWD_DEL          0.000                  2.749  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.wdo0
                                                                                   NET DELAY             0.000                  2.749  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.dpram_inst_0/DI0->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_addr_r_0__I_0.dpram_inst_0/DO0
                                              SLICE_R49C112A                       QWDTOF0_DEL           1.010                  3.759  2
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/out_raw[0]
                                                                                   NET DELAY             0.261                  4.020  2
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_ctrl_fifo_rd_I_0_2_4_lut_4_lut/C->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_ctrl_fifo_rd_I_0_2_4_lut_4_lut/Z
                                              SLICE_R50C112D                       CTOF_DEL              0.213                  4.233  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/wr_req_valid_nxt
                                                                                   NET DELAY             0.000                  4.233  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_req_valid_c.ff_inst/DF
                                                                                   ENDPOINT              0.000                  4.233  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_req_valid_c.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11549/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.408,
            "delay":0.316
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.714,
            "delay":0.306
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.714,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-2.163,
            "delay":-2.878
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.543,
            "delay":0.620
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.543,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-1.319,
            "delay":0.224
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.922,
            "delay":0.397
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.330,
            "delay":2.253
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.330,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
                                                                                   CONSTRAINT            0.000                  0.092  1
    pll_refclk_i                              eval_top                             CLOCK LATENCY         0.000                  0.092  1
    pll_refclk_i                                                                   NET DELAY             0.000                  0.092  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL              0.316                  0.408  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY             0.306                  0.714  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                           0.000                  0.714  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                          -2.878                 -2.163  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY             0.620                 -1.543  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL           0.000                 -1.543  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY             0.224                 -1.319  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL         0.397                 -0.922  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY             2.253                  1.330  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_req_valid_c.ff_inst/CLK
                                                                                   CLOCK PIN             0.000                  1.330  1
                                                                                   Uncertainty        -(0.000)                  1.330
                                                                                   Common Path Skew      0.000                  1.330
                                                                                   Setup time        -(-0.058)                  1.388
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Required Time                                                                                                               1.388
    Arrival Time                                                                                                             -(4.232)
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Path Slack  (Failed)                                                                                                       -2.844

    ++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WDO1  (SLICE_R56C111C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_data_last.ff_inst/DF  (SLICE_R54C111C)
    Source Clock     : clk_w (R)
    Destination Clock: sclk_o (R)
    Logic Level      : 3
    Delay Ratio      : 17.3% (route), 82.7% (logic)
    Clock Skew       : -1.511 ns
    Setup Constraint : 0.092 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -2.838 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_8.SLICE_2787/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":2.736,
            "delay":2.736
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":2.736,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.179,
            "delay":-2.557
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.749,
            "delay":2.570
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.749,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY         0.000                  0.000  3
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY             2.736                  2.736  3
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                           0.000                  2.736  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                          -2.557                  0.179  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY             2.570                  2.749  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WCK
                                                                                   CLOCK PIN             0.000                  2.749  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WDO1",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_8.SLICE_2787/WDO1"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_data_last.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11551/DI0"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_8.SLICE_2787/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WDO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_8.SLICE_2787/WDO1"
            },
            "arrive":2.749,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.wdo1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_8.wdo1"
            },
            "arrive":2.749,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.dpram_inst_0/DI1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2788/WDI1"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.dpram_inst_0/DO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2788/F1"
            },
            "arrive":3.759,
            "delay":1.010
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[129]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.out_raw[129]"
            },
            "arrive":4.014,
            "delay":0.255
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/i393_4_lut_4_lut/C",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11551/D0"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/i393_4_lut_4_lut/Z",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11551/F0"
            },
            "arrive":4.227,
            "delay":0.213
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_last_N_13317",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.wr_last_N_13317"
            },
            "arrive":4.227,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":4.227,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.ramw_inst/WDO1
                                              SLICE_R56C111C                       CLKTOQWD_DEL          0.000                  2.749  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.wdo1
                                                                                   NET DELAY             0.000                  2.749  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.dpram_inst_0/DI1->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_8.dpram_inst_0/DO1
                                              SLICE_R56C111A                       QWDTOF1_DEL           1.010                  3.759  2
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[129]
                                                                                   NET DELAY             0.255                  4.014  2
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/i393_4_lut_4_lut/C->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/i393_4_lut_4_lut/Z
                                              SLICE_R54C111C                       CTOF_DEL              0.213                  4.227  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_last_N_13317
                                                                                   NET DELAY             0.000                  4.227  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_data_last.ff_inst/DF
                                                                                   ENDPOINT              0.000                  4.227  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_data_last.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.SLICE_11551/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.408,
            "delay":0.316
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.714,
            "delay":0.306
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.714,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-2.163,
            "delay":-2.878
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.543,
            "delay":0.620
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.543,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-1.319,
            "delay":0.224
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.922,
            "delay":0.397
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.330,
            "delay":2.253
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.330,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
                                                                                   CONSTRAINT            0.000                  0.092  1
    pll_refclk_i                              eval_top                             CLOCK LATENCY         0.000                  0.092  1
    pll_refclk_i                                                                   NET DELAY             0.000                  0.092  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL              0.316                  0.408  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY             0.306                  0.714  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                           0.000                  0.714  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                          -2.878                 -2.163  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY             0.620                 -1.543  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL           0.000                 -1.543  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY             0.224                 -1.319  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL         0.397                 -0.922  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY             2.253                  1.330  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/wr_data_last.ff_inst/CLK
                                                                                   CLOCK PIN             0.000                  1.330  1
                                                                                   Uncertainty        -(0.000)                  1.330
                                                                                   Common Path Skew      0.000                  1.330
                                                                                   Setup time        -(-0.058)                  1.388
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Required Time                                                                                                               1.388
    Arrival Time                                                                                                             -(4.226)
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Path Slack  (Failed)                                                                                                       -2.838

    ++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.ramw_inst/WDO1  (SLICE_R63C118C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i42.ff_inst/DF  (SLICE_R63C118A)
    Source Clock     : clk_w (R)
    Destination Clock: sclk_o (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : -1.511 ns
    Setup Constraint : 0.092 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -2.371 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_30.SLICE_2727/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":2.736,
            "delay":2.736
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":2.736,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.179,
            "delay":-2.557
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.749,
            "delay":2.570
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.749,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY         0.000                  0.000  3
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY             2.736                  2.736  3
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                           0.000                  2.736  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                          -2.557                  0.179  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY             2.570                  2.749  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.ramw_inst/WCK
                                                                                   CLOCK PIN             0.000                  2.749  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.ramw_inst/WDO1",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_30.SLICE_2727/WDO1"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i42.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2728/DI1"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_30.SLICE_2727/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.ramw_inst/WDO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_30.SLICE_2727/WDO1"
            },
            "arrive":2.749,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.wdo1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_30.wdo1"
            },
            "arrive":2.749,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.dpram_inst_0/DI1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2728/WDI1"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.dpram_inst_0/DO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2728/F1"
            },
            "arrive":3.759,
            "delay":1.010
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[41]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.out_raw[41]"
            },
            "arrive":3.759,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":3.759,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.ramw_inst/WDO1
                                              SLICE_R63C118C                       CLKTOQWD_DEL          0.000                  2.749  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.wdo1
                                                                                   NET DELAY             0.000                  2.749  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.dpram_inst_0/DI1->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_30.dpram_inst_0/DO1
                                              SLICE_R63C118A                       QWDTOF1_DEL           1.010                  3.759  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[41]
                                                                                   NET DELAY             0.000                  3.759  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i42.ff_inst/DF
                                                                                   ENDPOINT              0.000                  3.759  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i41.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2728/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.408,
            "delay":0.316
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.714,
            "delay":0.306
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.714,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-2.163,
            "delay":-2.878
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.543,
            "delay":0.620
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.543,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-1.319,
            "delay":0.224
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.922,
            "delay":0.397
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.330,
            "delay":2.253
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.330,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
                                                                                   CONSTRAINT            0.000                  0.092  1
    pll_refclk_i                              eval_top                             CLOCK LATENCY         0.000                  0.092  1
    pll_refclk_i                                                                   NET DELAY             0.000                  0.092  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL              0.316                  0.408  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY             0.306                  0.714  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                           0.000                  0.714  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                          -2.878                 -2.163  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY             0.620                 -1.543  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL           0.000                 -1.543  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY             0.224                 -1.319  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL         0.397                 -0.922  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY             2.253                  1.330  6014
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i41.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i42.ff_inst/CLK}
                                                                                   CLOCK PIN             0.000                  1.330  1
                                                                                   Uncertainty        -(0.000)                  1.330
                                                                                   Common Path Skew      0.000                  1.330
                                                                                   Setup time        -(-0.057)                  1.387
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Required Time                                                                                                               1.387
    Arrival Time                                                                                                             -(3.758)
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Path Slack  (Failed)                                                                                                       -2.371

    ++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WDO3  (SLICE_R58C118C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i84.ff_inst/DF  (SLICE_R58C118B)
    Source Clock     : clk_w (R)
    Destination Clock: sclk_o (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : -1.511 ns
    Setup Constraint : 0.092 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -2.371 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_20.SLICE_2724/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":2.736,
            "delay":2.736
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":2.736,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.179,
            "delay":-2.557
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.749,
            "delay":2.570
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.749,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY         0.000                  0.000  3
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY             2.736                  2.736  3
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                           0.000                  2.736  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                          -2.557                  0.179  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY             2.570                  2.749  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WCK
                                                                                   CLOCK PIN             0.000                  2.749  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WDO3",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_20.SLICE_2724/WDO3"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i84.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2726/DI1"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_20.SLICE_2724/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WDO3",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_20.SLICE_2724/WDO3"
            },
            "arrive":2.749,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.wdo3",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_20.wdo3"
            },
            "arrive":2.749,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.dpram_inst_1/DI1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2726/WDI1"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.dpram_inst_1/DO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2726/F1"
            },
            "arrive":3.759,
            "delay":1.010
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[83]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.out_raw[83]"
            },
            "arrive":3.759,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":3.759,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WDO3
                                              SLICE_R58C118C                       CLKTOQWD_DEL          0.000                  2.749  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.wdo3
                                                                                   NET DELAY             0.000                  2.749  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.dpram_inst_1/DI1->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.dpram_inst_1/DO1
                                              SLICE_R58C118B                       QWDTOF1_DEL           1.010                  3.759  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[83]
                                                                                   NET DELAY             0.000                  3.759  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i84.ff_inst/DF
                                                                                   ENDPOINT              0.000                  3.759  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i83.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2726/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.408,
            "delay":0.316
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.714,
            "delay":0.306
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.714,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-2.163,
            "delay":-2.878
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.543,
            "delay":0.620
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.543,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-1.319,
            "delay":0.224
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.922,
            "delay":0.397
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.330,
            "delay":2.253
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.330,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
                                                                                   CONSTRAINT            0.000                  0.092  1
    pll_refclk_i                              eval_top                             CLOCK LATENCY         0.000                  0.092  1
    pll_refclk_i                                                                   NET DELAY             0.000                  0.092  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL              0.316                  0.408  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY             0.306                  0.714  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                           0.000                  0.714  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                          -2.878                 -2.163  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY             0.620                 -1.543  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL           0.000                 -1.543  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY             0.224                 -1.319  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL         0.397                 -0.922  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY             2.253                  1.330  6014
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i83.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i84.ff_inst/CLK}
                                                                                   CLOCK PIN             0.000                  1.330  1
                                                                                   Uncertainty        -(0.000)                  1.330
                                                                                   Common Path Skew      0.000                  1.330
                                                                                   Setup time        -(-0.057)                  1.387
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Required Time                                                                                                               1.387
    Arrival Time                                                                                                             -(3.758)
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Path Slack  (Failed)                                                                                                       -2.371

    ++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WDO1  (SLICE_R58C118C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i82.ff_inst/DF  (SLICE_R58C118A)
    Source Clock     : clk_w (R)
    Destination Clock: sclk_o (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : -1.511 ns
    Setup Constraint : 0.092 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -2.371 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_20.SLICE_2724/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":2.736,
            "delay":2.736
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":2.736,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.179,
            "delay":-2.557
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.749,
            "delay":2.570
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.749,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY         0.000                  0.000  3
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY             2.736                  2.736  3
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                           0.000                  2.736  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                          -2.557                  0.179  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY             2.570                  2.749  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WCK
                                                                                   CLOCK PIN             0.000                  2.749  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WDO1",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_20.SLICE_2724/WDO1"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i82.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2725/DI1"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_20.SLICE_2724/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WDO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_20.SLICE_2724/WDO1"
            },
            "arrive":2.749,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.wdo1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_20.wdo1"
            },
            "arrive":2.749,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.dpram_inst_0/DI1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2725/WDI1"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.dpram_inst_0/DO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2725/F1"
            },
            "arrive":3.759,
            "delay":1.010
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[81]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.out_raw[81]"
            },
            "arrive":3.759,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":3.759,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.ramw_inst/WDO1
                                              SLICE_R58C118C                       CLKTOQWD_DEL          0.000                  2.749  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.wdo1
                                                                                   NET DELAY             0.000                  2.749  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.dpram_inst_0/DI1->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_20.dpram_inst_0/DO1
                                              SLICE_R58C118A                       QWDTOF1_DEL           1.010                  3.759  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[81]
                                                                                   NET DELAY             0.000                  3.759  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i82.ff_inst/DF
                                                                                   ENDPOINT              0.000                  3.759  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i81.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2725/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.408,
            "delay":0.316
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.714,
            "delay":0.306
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.714,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-2.163,
            "delay":-2.878
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.543,
            "delay":0.620
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.543,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-1.319,
            "delay":0.224
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.922,
            "delay":0.397
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.330,
            "delay":2.253
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.330,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
                                                                                   CONSTRAINT            0.000                  0.092  1
    pll_refclk_i                              eval_top                             CLOCK LATENCY         0.000                  0.092  1
    pll_refclk_i                                                                   NET DELAY             0.000                  0.092  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL              0.316                  0.408  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY             0.306                  0.714  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                           0.000                  0.714  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                          -2.878                 -2.163  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY             0.620                 -1.543  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL           0.000                 -1.543  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY             0.224                 -1.319  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL         0.397                 -0.922  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY             2.253                  1.330  6014
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i81.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i82.ff_inst/CLK}
                                                                                   CLOCK PIN             0.000                  1.330  1
                                                                                   Uncertainty        -(0.000)                  1.330
                                                                                   Common Path Skew      0.000                  1.330
                                                                                   Setup time        -(-0.057)                  1.387
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Required Time                                                                                                               1.387
    Arrival Time                                                                                                             -(3.758)
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Path Slack  (Failed)                                                                                                       -2.371

    ++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WDO3  (SLICE_R63C116C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i48.ff_inst/DF  (SLICE_R63C116B)
    Source Clock     : clk_w (R)
    Destination Clock: sclk_o (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : -1.511 ns
    Setup Constraint : 0.092 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -2.371 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_29.SLICE_2721/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":2.736,
            "delay":2.736
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":2.736,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.179,
            "delay":-2.557
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.749,
            "delay":2.570
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.749,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY         0.000                  0.000  3
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY             2.736                  2.736  3
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                           0.000                  2.736  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                          -2.557                  0.179  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY             2.570                  2.749  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WCK
                                                                                   CLOCK PIN             0.000                  2.749  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WDO3",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_29.SLICE_2721/WDO3"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i48.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2723/DI1"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_29.SLICE_2721/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WDO3",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_29.SLICE_2721/WDO3"
            },
            "arrive":2.749,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.wdo3",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_29.wdo3"
            },
            "arrive":2.749,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.dpram_inst_1/DI1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2723/WDI1"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.dpram_inst_1/DO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2723/F1"
            },
            "arrive":3.759,
            "delay":1.010
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[47]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.out_raw[47]"
            },
            "arrive":3.759,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":3.759,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WDO3
                                              SLICE_R63C116C                       CLKTOQWD_DEL          0.000                  2.749  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.wdo3
                                                                                   NET DELAY             0.000                  2.749  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.dpram_inst_1/DI1->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.dpram_inst_1/DO1
                                              SLICE_R63C116B                       QWDTOF1_DEL           1.010                  3.759  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[47]
                                                                                   NET DELAY             0.000                  3.759  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i48.ff_inst/DF
                                                                                   ENDPOINT              0.000                  3.759  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i47.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2723/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.408,
            "delay":0.316
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.714,
            "delay":0.306
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.714,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-2.163,
            "delay":-2.878
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.543,
            "delay":0.620
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.543,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-1.319,
            "delay":0.224
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.922,
            "delay":0.397
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.330,
            "delay":2.253
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.330,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
                                                                                   CONSTRAINT            0.000                  0.092  1
    pll_refclk_i                              eval_top                             CLOCK LATENCY         0.000                  0.092  1
    pll_refclk_i                                                                   NET DELAY             0.000                  0.092  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL              0.316                  0.408  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY             0.306                  0.714  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                           0.000                  0.714  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                          -2.878                 -2.163  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY             0.620                 -1.543  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL           0.000                 -1.543  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY             0.224                 -1.319  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL         0.397                 -0.922  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY             2.253                  1.330  6014
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i47.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i48.ff_inst/CLK}
                                                                                   CLOCK PIN             0.000                  1.330  1
                                                                                   Uncertainty        -(0.000)                  1.330
                                                                                   Common Path Skew      0.000                  1.330
                                                                                   Setup time        -(-0.057)                  1.387
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Required Time                                                                                                               1.387
    Arrival Time                                                                                                             -(3.758)
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Path Slack  (Failed)                                                                                                       -2.371

    ++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WDO1  (SLICE_R63C116C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i46.ff_inst/DF  (SLICE_R63C116A)
    Source Clock     : clk_w (R)
    Destination Clock: sclk_o (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : -1.511 ns
    Setup Constraint : 0.092 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -2.371 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_29.SLICE_2721/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":2.736,
            "delay":2.736
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":2.736,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.179,
            "delay":-2.557
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.749,
            "delay":2.570
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.749,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY         0.000                  0.000  3
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY             2.736                  2.736  3
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                           0.000                  2.736  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                          -2.557                  0.179  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY             2.570                  2.749  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WCK
                                                                                   CLOCK PIN             0.000                  2.749  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WDO1",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_29.SLICE_2721/WDO1"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i46.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2722/DI1"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_29.SLICE_2721/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WDO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_29.SLICE_2721/WDO1"
            },
            "arrive":2.749,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.wdo1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_29.wdo1"
            },
            "arrive":2.749,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.dpram_inst_0/DI1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2722/WDI1"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.dpram_inst_0/DO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2722/F1"
            },
            "arrive":3.759,
            "delay":1.010
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[45]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.out_raw[45]"
            },
            "arrive":3.759,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":3.759,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.ramw_inst/WDO1
                                              SLICE_R63C116C                       CLKTOQWD_DEL          0.000                  2.749  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.wdo1
                                                                                   NET DELAY             0.000                  2.749  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.dpram_inst_0/DI1->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_29.dpram_inst_0/DO1
                                              SLICE_R63C116A                       QWDTOF1_DEL           1.010                  3.759  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[45]
                                                                                   NET DELAY             0.000                  3.759  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i46.ff_inst/DF
                                                                                   ENDPOINT              0.000                  3.759  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i45.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2722/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.408,
            "delay":0.316
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.714,
            "delay":0.306
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.714,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-2.163,
            "delay":-2.878
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.543,
            "delay":0.620
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.543,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-1.319,
            "delay":0.224
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.922,
            "delay":0.397
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.330,
            "delay":2.253
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.330,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
                                                                                   CONSTRAINT            0.000                  0.092  1
    pll_refclk_i                              eval_top                             CLOCK LATENCY         0.000                  0.092  1
    pll_refclk_i                                                                   NET DELAY             0.000                  0.092  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL              0.316                  0.408  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY             0.306                  0.714  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                           0.000                  0.714  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                          -2.878                 -2.163  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY             0.620                 -1.543  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL           0.000                 -1.543  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY             0.224                 -1.319  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL         0.397                 -0.922  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY             2.253                  1.330  6014
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i45.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i46.ff_inst/CLK}
                                                                                   CLOCK PIN             0.000                  1.330  1
                                                                                   Uncertainty        -(0.000)                  1.330
                                                                                   Common Path Skew      0.000                  1.330
                                                                                   Setup time        -(-0.057)                  1.387
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Required Time                                                                                                               1.387
    Arrival Time                                                                                                             -(3.758)
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Path Slack  (Failed)                                                                                                       -2.371

    ++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WDO3  (SLICE_R60C111C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i56.ff_inst/DF  (SLICE_R60C111B)
    Source Clock     : clk_w (R)
    Destination Clock: sclk_o (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : -1.511 ns
    Setup Constraint : 0.092 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -2.371 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_27.SLICE_2718/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":2.736,
            "delay":2.736
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":2.736,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.179,
            "delay":-2.557
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.749,
            "delay":2.570
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.749,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY         0.000                  0.000  3
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY             2.736                  2.736  3
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                           0.000                  2.736  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                          -2.557                  0.179  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY             2.570                  2.749  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WCK
                                                                                   CLOCK PIN             0.000                  2.749  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WDO3",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_27.SLICE_2718/WDO3"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i56.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2720/DI1"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_27.SLICE_2718/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WDO3",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_27.SLICE_2718/WDO3"
            },
            "arrive":2.749,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.wdo3",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_27.wdo3"
            },
            "arrive":2.749,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.dpram_inst_1/DI1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2720/WDI1"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.dpram_inst_1/DO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2720/F1"
            },
            "arrive":3.759,
            "delay":1.010
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[55]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.out_raw[55]"
            },
            "arrive":3.759,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":3.759,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WDO3
                                              SLICE_R60C111C                       CLKTOQWD_DEL          0.000                  2.749  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.wdo3
                                                                                   NET DELAY             0.000                  2.749  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.dpram_inst_1/DI1->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.dpram_inst_1/DO1
                                              SLICE_R60C111B                       QWDTOF1_DEL           1.010                  3.759  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[55]
                                                                                   NET DELAY             0.000                  3.759  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i56.ff_inst/DF
                                                                                   ENDPOINT              0.000                  3.759  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i55.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2720/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.408,
            "delay":0.316
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.714,
            "delay":0.306
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.714,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-2.163,
            "delay":-2.878
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.543,
            "delay":0.620
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.543,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-1.319,
            "delay":0.224
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.922,
            "delay":0.397
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.330,
            "delay":2.253
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.330,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
                                                                                   CONSTRAINT            0.000                  0.092  1
    pll_refclk_i                              eval_top                             CLOCK LATENCY         0.000                  0.092  1
    pll_refclk_i                                                                   NET DELAY             0.000                  0.092  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL              0.316                  0.408  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY             0.306                  0.714  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                           0.000                  0.714  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                          -2.878                 -2.163  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY             0.620                 -1.543  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL           0.000                 -1.543  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY             0.224                 -1.319  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL         0.397                 -0.922  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY             2.253                  1.330  6014
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i55.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i56.ff_inst/CLK}
                                                                                   CLOCK PIN             0.000                  1.330  1
                                                                                   Uncertainty        -(0.000)                  1.330
                                                                                   Common Path Skew      0.000                  1.330
                                                                                   Setup time        -(-0.057)                  1.387
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Required Time                                                                                                               1.387
    Arrival Time                                                                                                             -(3.758)
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Path Slack  (Failed)                                                                                                       -2.371

    ++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WDO1  (SLICE_R60C111C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i54.ff_inst/DF  (SLICE_R60C111A)
    Source Clock     : clk_w (R)
    Destination Clock: sclk_o (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : -1.511 ns
    Setup Constraint : 0.092 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -2.371 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_27.SLICE_2718/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":2.736,
            "delay":2.736
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":2.736,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.179,
            "delay":-2.557
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.749,
            "delay":2.570
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.749,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY         0.000                  0.000  3
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY             2.736                  2.736  3
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                           0.000                  2.736  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                          -2.557                  0.179  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY             2.570                  2.749  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WCK
                                                                                   CLOCK PIN             0.000                  2.749  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WDO1",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_27.SLICE_2718/WDO1"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i54.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2719/DI1"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_27.SLICE_2718/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WDO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_27.SLICE_2718/WDO1"
            },
            "arrive":2.749,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.wdo1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.wr_addr_r_0__I_0_27.wdo1"
            },
            "arrive":2.749,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.dpram_inst_0/DI1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2719/WDI1"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.dpram_inst_0/DO1",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2719/F1"
            },
            "arrive":3.759,
            "delay":1.010
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[53]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.out_raw[53]"
            },
            "arrive":3.759,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":3.759,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.ramw_inst/WDO1
                                              SLICE_R60C111C                       CLKTOQWD_DEL          0.000                  2.749  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.wdo1
                                                                                   NET DELAY             0.000                  2.749  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.dpram_inst_0/DI1->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/wr_addr_r_0__I_0_27.dpram_inst_0/DO1
                                              SLICE_R60C111A                       QWDTOF1_DEL           1.010                  3.759  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_raw[53]
                                                                                   NET DELAY             0.000                  3.759  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i54.ff_inst/DF
                                                                                   ENDPOINT              0.000                  3.759  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i53.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fifo_dc.SLICE_2719/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.092,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.408,
            "delay":0.316
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.714,
            "delay":0.306
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.714,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-2.163,
            "delay":-2.878
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.543,
            "delay":0.620
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.543,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-1.319,
            "delay":0.224
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.922,
            "delay":0.397
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.330,
            "delay":2.253
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.330,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr       Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
                                                                                   CONSTRAINT            0.000                  0.092  1
    pll_refclk_i                              eval_top                             CLOCK LATENCY         0.000                  0.092  1
    pll_refclk_i                                                                   NET DELAY             0.000                  0.092  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL              0.316                  0.408  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY             0.306                  0.714  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                           0.000                  0.714  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                          -2.878                 -2.163  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY             0.620                 -1.543  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL           0.000                 -1.543  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY             0.224                 -1.319  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL         0.397                 -0.922  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY             2.253                  1.330  6014
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i53.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/out_buffer_i54.ff_inst/CLK}
                                                                                   CLOCK PIN             0.000                  1.330  1
                                                                                   Uncertainty        -(0.000)                  1.330
                                                                                   Common Path Skew      0.000                  1.330
                                                                                   Setup time        -(-0.057)                  1.387
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Required Time                                                                                                               1.387
    Arrival Time                                                                                                             -(3.758)
    ----------------------------------------  -----------------------------------  ----------------  ---------  ---------------------  ------
    Path Slack  (Failed)                                                                                                       -2.371

    +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
                        End of Detailed Report for timing paths
    +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    ##########################################################

    4  Hold at Speed Grade m Corner at 0 Degrees
    4.1  Endpoint slacks
    -------------------------------------------------------
              Listing 10 End Points          |    Slack
    -------------------------------------------------------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i19.ff_inst/DF
                                             |   -0.472 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i17.ff_inst/DF
                                             |   -0.472 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i11.ff_inst/DF
                                             |   -0.472 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i9.ff_inst/DF
                                             |   -0.472 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i23.ff_inst/DF
                                             |   -0.472 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i21.ff_inst/DF
                                             |   -0.472 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i3.ff_inst/DF
                                             |   -0.472 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i1.ff_inst/DF
                                             |   -0.472 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i7.ff_inst/DF
                                             |   -0.472 ns
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i5.ff_inst/DF
                                             |   -0.472 ns
    -------------------------------------------------------
                                             |
    Hold # of endpoints with negative slack: |          19
                                             |
    -------------------------------------------------------

    4.2  Detailed Report

    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Detail report of critical paths

    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

     +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
                        Detailed Report for timing paths
     +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

     ++++Path 1  ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.ramw_inst/WDO2  (SLICE_R21C82C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i19.ff_inst/DF  (SLICE_R21C82B)
    Source Clock     : sclk_o (R)
    Destination Clock: clk_w (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : 0.910 ns
    Hold Constraint  : 0.000 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -0.472 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_3.SLICE_2875/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.000,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.262,
            "delay":0.262
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.502,
            "delay":0.240
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.502,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-1.611,
            "delay":-2.113
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.096,
            "delay":0.515
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.096,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-0.947,
            "delay":0.149
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.505,
            "delay":0.442
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.131,
            "delay":1.637
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.131,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    pll_refclk_i                              eval_top                             CLOCK LATENCY      0.000                  0.000  1
    pll_refclk_i                                                                   NET DELAY          0.000                  0.000  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL           0.262                  0.262  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY          0.240                  0.502  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                        0.000                  0.502  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                       -2.113                 -1.611  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY          0.515                 -1.096  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL        0.000                 -1.096  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY          0.149                 -0.947  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL      0.442                 -0.505  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY          1.637                  1.131  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.ramw_inst/WCK
                                                                                   CLOCK PIN          0.000                  1.131  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.ramw_inst/WDO2",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_3.SLICE_2875/WDO2"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i19.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2877/DI0"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_3.SLICE_2875/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.ramw_inst/WDO2",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_3.SLICE_2875/WDO2"
            },
            "arrive":1.132,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.wdo2",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_3.wdo2"
            },
            "arrive":1.132,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.dpram_inst_1/DI0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2877/WDI0"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.dpram_inst_1/DO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2877/F0"
            },
            "arrive":1.684,
            "delay":0.552
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_rddata[18]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_rddata[18]"
            },
            "arrive":1.684,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.684,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.ramw_inst/WDO2
                                              SLICE_R21C82C                        CLKTOQWD_DEL       0.000                  1.132  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.wdo2
                                                                                   NET DELAY          0.000                  1.132  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.dpram_inst_1/DI0->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.dpram_inst_1/DO0
                                              SLICE_R21C82B                        QWDTOF0_DEL        0.552                  1.684  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_rddata[18]
                                                                                   NET DELAY          0.000                  1.684  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i19.ff_inst/DF
                                                                                   ENDPOINT           0.000                  1.684  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i19.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2877/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.000,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":1.994,
            "delay":1.994
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":1.994,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.153,
            "delay":-1.841
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.042,
            "delay":1.889
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.042,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
                                                                                   CONSTRAINT         0.000                  0.000  1
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY      0.000                  0.000  4
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY          1.994                  1.994  4
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                        0.000                  1.994  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                       -1.841                  0.153  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY          1.889                  2.042  1922
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i19.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i20.ff_inst/CLK}
                                                                                   CLOCK PIN          0.000                  2.042  1
                                                                                   Uncertainty        0.000                  2.042
                                                                                   Common Path Skew   0.000                  2.042
                                                                                   Hold time          0.114                  2.156
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    Required Time                                                                                                           -2.156
    Arrival Time                                                                                                             1.683
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    Path Slack  (Failed)                                                                                                    -0.472

    ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.ramw_inst/WDO0  (SLICE_R21C82C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i17.ff_inst/DF  (SLICE_R21C82A)
    Source Clock     : sclk_o (R)
    Destination Clock: clk_w (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : 0.910 ns
    Hold Constraint  : 0.000 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -0.472 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_3.SLICE_2875/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.000,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.262,
            "delay":0.262
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.502,
            "delay":0.240
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.502,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-1.611,
            "delay":-2.113
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.096,
            "delay":0.515
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.096,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-0.947,
            "delay":0.149
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.505,
            "delay":0.442
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.131,
            "delay":1.637
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.131,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    pll_refclk_i                              eval_top                             CLOCK LATENCY      0.000                  0.000  1
    pll_refclk_i                                                                   NET DELAY          0.000                  0.000  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL           0.262                  0.262  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY          0.240                  0.502  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                        0.000                  0.502  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                       -2.113                 -1.611  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY          0.515                 -1.096  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL        0.000                 -1.096  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY          0.149                 -0.947  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL      0.442                 -0.505  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY          1.637                  1.131  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.ramw_inst/WCK
                                                                                   CLOCK PIN          0.000                  1.131  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.ramw_inst/WDO0",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_3.SLICE_2875/WDO0"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i17.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2876/DI0"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_3.SLICE_2875/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.ramw_inst/WDO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_3.SLICE_2875/WDO0"
            },
            "arrive":1.132,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.wdo0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_3.wdo0"
            },
            "arrive":1.132,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.dpram_inst_0/DI0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2876/WDI0"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.dpram_inst_0/DO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2876/F0"
            },
            "arrive":1.684,
            "delay":0.552
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_rddata[16]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_rddata[16]"
            },
            "arrive":1.684,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.684,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.ramw_inst/WDO0
                                              SLICE_R21C82C                        CLKTOQWD_DEL       0.000                  1.132  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.wdo0
                                                                                   NET DELAY          0.000                  1.132  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.dpram_inst_0/DI0->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_3.dpram_inst_0/DO0
                                              SLICE_R21C82A                        QWDTOF0_DEL        0.552                  1.684  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_rddata[16]
                                                                                   NET DELAY          0.000                  1.684  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i17.ff_inst/DF
                                                                                   ENDPOINT           0.000                  1.684  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i17.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2876/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.000,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":1.994,
            "delay":1.994
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":1.994,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.153,
            "delay":-1.841
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.042,
            "delay":1.889
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.042,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
                                                                                   CONSTRAINT         0.000                  0.000  1
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY      0.000                  0.000  4
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY          1.994                  1.994  4
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                        0.000                  1.994  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                       -1.841                  0.153  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY          1.889                  2.042  1922
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i17.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i18.ff_inst/CLK}
                                                                                   CLOCK PIN          0.000                  2.042  1
                                                                                   Uncertainty        0.000                  2.042
                                                                                   Common Path Skew   0.000                  2.042
                                                                                   Hold time          0.114                  2.156
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    Required Time                                                                                                           -2.156
    Arrival Time                                                                                                             1.683
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    Path Slack  (Failed)                                                                                                    -0.472

    ++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.ramw_inst/WDO2  (SLICE_R22C82C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i11.ff_inst/DF  (SLICE_R22C82B)
    Source Clock     : sclk_o (R)
    Destination Clock: clk_w (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : 0.910 ns
    Hold Constraint  : 0.000 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -0.472 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_5.SLICE_2872/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.000,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.262,
            "delay":0.262
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.502,
            "delay":0.240
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.502,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-1.611,
            "delay":-2.113
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.096,
            "delay":0.515
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.096,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-0.947,
            "delay":0.149
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.505,
            "delay":0.442
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.131,
            "delay":1.637
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.131,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    pll_refclk_i                              eval_top                             CLOCK LATENCY      0.000                  0.000  1
    pll_refclk_i                                                                   NET DELAY          0.000                  0.000  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL           0.262                  0.262  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY          0.240                  0.502  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                        0.000                  0.502  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                       -2.113                 -1.611  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY          0.515                 -1.096  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL        0.000                 -1.096  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY          0.149                 -0.947  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL      0.442                 -0.505  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY          1.637                  1.131  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.ramw_inst/WCK
                                                                                   CLOCK PIN          0.000                  1.131  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.ramw_inst/WDO2",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_5.SLICE_2872/WDO2"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i11.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2874/DI0"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_5.SLICE_2872/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.ramw_inst/WDO2",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_5.SLICE_2872/WDO2"
            },
            "arrive":1.132,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.wdo2",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_5.wdo2"
            },
            "arrive":1.132,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.dpram_inst_1/DI0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2874/WDI0"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.dpram_inst_1/DO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2874/F0"
            },
            "arrive":1.684,
            "delay":0.552
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_rddata[10]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_rddata[10]"
            },
            "arrive":1.684,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.684,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.ramw_inst/WDO2
                                              SLICE_R22C82C                        CLKTOQWD_DEL       0.000                  1.132  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.wdo2
                                                                                   NET DELAY          0.000                  1.132  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.dpram_inst_1/DI0->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.dpram_inst_1/DO0
                                              SLICE_R22C82B                        QWDTOF0_DEL        0.552                  1.684  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_rddata[10]
                                                                                   NET DELAY          0.000                  1.684  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i11.ff_inst/DF
                                                                                   ENDPOINT           0.000                  1.684  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i11.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2874/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.000,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":1.994,
            "delay":1.994
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":1.994,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.153,
            "delay":-1.841
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.042,
            "delay":1.889
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.042,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
                                                                                   CONSTRAINT         0.000                  0.000  1
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY      0.000                  0.000  4
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY          1.994                  1.994  4
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                        0.000                  1.994  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                       -1.841                  0.153  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY          1.889                  2.042  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i11.ff_inst/CLK
                                                                                   CLOCK PIN          0.000                  2.042  1
                                                                                   Uncertainty        0.000                  2.042
                                                                                   Common Path Skew   0.000                  2.042
                                                                                   Hold time          0.114                  2.156
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    Required Time                                                                                                           -2.156
    Arrival Time                                                                                                             1.683
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    Path Slack  (Failed)                                                                                                    -0.472

    ++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.ramw_inst/WDO0  (SLICE_R22C82C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i9.ff_inst/DF  (SLICE_R22C82A)
    Source Clock     : sclk_o (R)
    Destination Clock: clk_w (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : 0.910 ns
    Hold Constraint  : 0.000 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -0.472 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_5.SLICE_2872/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.000,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.262,
            "delay":0.262
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.502,
            "delay":0.240
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.502,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-1.611,
            "delay":-2.113
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.096,
            "delay":0.515
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.096,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-0.947,
            "delay":0.149
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.505,
            "delay":0.442
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.131,
            "delay":1.637
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.131,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    pll_refclk_i                              eval_top                             CLOCK LATENCY      0.000                  0.000  1
    pll_refclk_i                                                                   NET DELAY          0.000                  0.000  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL           0.262                  0.262  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY          0.240                  0.502  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                        0.000                  0.502  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                       -2.113                 -1.611  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY          0.515                 -1.096  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL        0.000                 -1.096  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY          0.149                 -0.947  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL      0.442                 -0.505  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY          1.637                  1.131  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.ramw_inst/WCK
                                                                                   CLOCK PIN          0.000                  1.131  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.ramw_inst/WDO0",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_5.SLICE_2872/WDO0"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i9.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2873/DI0"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_5.SLICE_2872/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.ramw_inst/WDO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_5.SLICE_2872/WDO0"
            },
            "arrive":1.132,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.wdo0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_5.wdo0"
            },
            "arrive":1.132,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.dpram_inst_0/DI0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2873/WDI0"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.dpram_inst_0/DO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2873/F0"
            },
            "arrive":1.684,
            "delay":0.552
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_rddata[8]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_rddata[8]"
            },
            "arrive":1.684,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.684,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.ramw_inst/WDO0
                                              SLICE_R22C82C                        CLKTOQWD_DEL       0.000                  1.132  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.wdo0
                                                                                   NET DELAY          0.000                  1.132  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.dpram_inst_0/DI0->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_5.dpram_inst_0/DO0
                                              SLICE_R22C82A                        QWDTOF0_DEL        0.552                  1.684  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_rddata[8]
                                                                                   NET DELAY          0.000                  1.684  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i9.ff_inst/DF
                                                                                   ENDPOINT           0.000                  1.684  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i9.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2873/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.000,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":1.994,
            "delay":1.994
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":1.994,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.153,
            "delay":-1.841
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.042,
            "delay":1.889
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.042,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
                                                                                   CONSTRAINT         0.000                  0.000  1
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY      0.000                  0.000  4
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY          1.994                  1.994  4
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                        0.000                  1.994  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                       -1.841                  0.153  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY          1.889                  2.042  1922
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i9.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i10.ff_inst/CLK}
                                                                                   CLOCK PIN          0.000                  2.042  1
                                                                                   Uncertainty        0.000                  2.042
                                                                                   Common Path Skew   0.000                  2.042
                                                                                   Hold time          0.114                  2.156
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    Required Time                                                                                                           -2.156
    Arrival Time                                                                                                             1.683
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    Path Slack  (Failed)                                                                                                    -0.472

    ++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.ramw_inst/WDO2  (SLICE_R21C83C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i23.ff_inst/DF  (SLICE_R21C83B)
    Source Clock     : sclk_o (R)
    Destination Clock: clk_w (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : 0.910 ns
    Hold Constraint  : 0.000 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -0.472 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_2.SLICE_2869/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.000,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.262,
            "delay":0.262
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.502,
            "delay":0.240
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.502,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-1.611,
            "delay":-2.113
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.096,
            "delay":0.515
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.096,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-0.947,
            "delay":0.149
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.505,
            "delay":0.442
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.131,
            "delay":1.637
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.131,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    pll_refclk_i                              eval_top                             CLOCK LATENCY      0.000                  0.000  1
    pll_refclk_i                                                                   NET DELAY          0.000                  0.000  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL           0.262                  0.262  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY          0.240                  0.502  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                        0.000                  0.502  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                       -2.113                 -1.611  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY          0.515                 -1.096  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL        0.000                 -1.096  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY          0.149                 -0.947  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL      0.442                 -0.505  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY          1.637                  1.131  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.ramw_inst/WCK
                                                                                   CLOCK PIN          0.000                  1.131  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.ramw_inst/WDO2",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_2.SLICE_2869/WDO2"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i23.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2871/DI0"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_2.SLICE_2869/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.ramw_inst/WDO2",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_2.SLICE_2869/WDO2"
            },
            "arrive":1.132,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.wdo2",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_2.wdo2"
            },
            "arrive":1.132,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.dpram_inst_1/DI0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2871/WDI0"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.dpram_inst_1/DO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2871/F0"
            },
            "arrive":1.684,
            "delay":0.552
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_rddata[22]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_rddata[22]"
            },
            "arrive":1.684,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.684,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.ramw_inst/WDO2
                                              SLICE_R21C83C                        CLKTOQWD_DEL       0.000                  1.132  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.wdo2
                                                                                   NET DELAY          0.000                  1.132  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.dpram_inst_1/DI0->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.dpram_inst_1/DO0
                                              SLICE_R21C83B                        QWDTOF0_DEL        0.552                  1.684  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_rddata[22]
                                                                                   NET DELAY          0.000                  1.684  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i23.ff_inst/DF
                                                                                   ENDPOINT           0.000                  1.684  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i23.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2871/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.000,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":1.994,
            "delay":1.994
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":1.994,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.153,
            "delay":-1.841
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.042,
            "delay":1.889
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.042,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
                                                                                   CONSTRAINT         0.000                  0.000  1
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY      0.000                  0.000  4
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY          1.994                  1.994  4
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                        0.000                  1.994  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                       -1.841                  0.153  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY          1.889                  2.042  1922
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i23.ff_inst/CLK
                                                                                   CLOCK PIN          0.000                  2.042  1
                                                                                   Uncertainty        0.000                  2.042
                                                                                   Common Path Skew   0.000                  2.042
                                                                                   Hold time          0.114                  2.156
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    Required Time                                                                                                           -2.156
    Arrival Time                                                                                                             1.683
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    Path Slack  (Failed)                                                                                                    -0.472

    ++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.ramw_inst/WDO0  (SLICE_R21C83C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i21.ff_inst/DF  (SLICE_R21C83A)
    Source Clock     : sclk_o (R)
    Destination Clock: clk_w (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : 0.910 ns
    Hold Constraint  : 0.000 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -0.472 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_2.SLICE_2869/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.000,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.262,
            "delay":0.262
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.502,
            "delay":0.240
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.502,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-1.611,
            "delay":-2.113
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.096,
            "delay":0.515
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.096,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-0.947,
            "delay":0.149
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.505,
            "delay":0.442
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.131,
            "delay":1.637
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.131,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    pll_refclk_i                              eval_top                             CLOCK LATENCY      0.000                  0.000  1
    pll_refclk_i                                                                   NET DELAY          0.000                  0.000  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL           0.262                  0.262  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY          0.240                  0.502  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                        0.000                  0.502  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                       -2.113                 -1.611  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY          0.515                 -1.096  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL        0.000                 -1.096  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY          0.149                 -0.947  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL      0.442                 -0.505  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY          1.637                  1.131  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.ramw_inst/WCK
                                                                                   CLOCK PIN          0.000                  1.131  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.ramw_inst/WDO0",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_2.SLICE_2869/WDO0"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i21.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2870/DI0"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_2.SLICE_2869/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.ramw_inst/WDO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_2.SLICE_2869/WDO0"
            },
            "arrive":1.132,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.wdo0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_2.wdo0"
            },
            "arrive":1.132,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.dpram_inst_0/DI0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2870/WDI0"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.dpram_inst_0/DO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2870/F0"
            },
            "arrive":1.684,
            "delay":0.552
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_rddata[20]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_rddata[20]"
            },
            "arrive":1.684,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.684,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.ramw_inst/WDO0
                                              SLICE_R21C83C                        CLKTOQWD_DEL       0.000                  1.132  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.wdo0
                                                                                   NET DELAY          0.000                  1.132  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.dpram_inst_0/DI0->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_2.dpram_inst_0/DO0
                                              SLICE_R21C83A                        QWDTOF0_DEL        0.552                  1.684  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_rddata[20]
                                                                                   NET DELAY          0.000                  1.684  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i21.ff_inst/DF
                                                                                   ENDPOINT           0.000                  1.684  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i21.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2870/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.000,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":1.994,
            "delay":1.994
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":1.994,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.153,
            "delay":-1.841
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.042,
            "delay":1.889
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.042,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
                                                                                   CONSTRAINT         0.000                  0.000  1
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY      0.000                  0.000  4
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY          1.994                  1.994  4
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                        0.000                  1.994  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                       -1.841                  0.153  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY          1.889                  2.042  1922
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i21.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i22.ff_inst/CLK}
                                                                                   CLOCK PIN          0.000                  2.042  1
                                                                                   Uncertainty        0.000                  2.042
                                                                                   Common Path Skew   0.000                  2.042
                                                                                   Hold time          0.114                  2.156
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    Required Time                                                                                                           -2.156
    Arrival Time                                                                                                             1.683
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    Path Slack  (Failed)                                                                                                    -0.472

    ++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.ramw_inst/WDO2  (SLICE_R23C82C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i3.ff_inst/DF  (SLICE_R23C82B)
    Source Clock     : sclk_o (R)
    Destination Clock: clk_w (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : 0.910 ns
    Hold Constraint  : 0.000 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -0.472 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0.SLICE_2866/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.000,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.262,
            "delay":0.262
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.502,
            "delay":0.240
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.502,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-1.611,
            "delay":-2.113
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.096,
            "delay":0.515
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.096,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-0.947,
            "delay":0.149
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.505,
            "delay":0.442
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.131,
            "delay":1.637
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.131,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    pll_refclk_i                              eval_top                             CLOCK LATENCY      0.000                  0.000  1
    pll_refclk_i                                                                   NET DELAY          0.000                  0.000  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL           0.262                  0.262  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY          0.240                  0.502  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                        0.000                  0.502  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                       -2.113                 -1.611  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY          0.515                 -1.096  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL        0.000                 -1.096  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY          0.149                 -0.947  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL      0.442                 -0.505  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY          1.637                  1.131  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.ramw_inst/WCK
                                                                                   CLOCK PIN          0.000                  1.131  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.ramw_inst/WDO2",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0.SLICE_2866/WDO2"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i3.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2868/DI0"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0.SLICE_2866/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.ramw_inst/WDO2",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0.SLICE_2866/WDO2"
            },
            "arrive":1.132,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.wdo2",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0.wdo2"
            },
            "arrive":1.132,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.dpram_inst_1/DI0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2868/WDI0"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.dpram_inst_1/DO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2868/F0"
            },
            "arrive":1.684,
            "delay":0.552
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_rddata[2]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_rddata[2]"
            },
            "arrive":1.684,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.684,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.ramw_inst/WDO2
                                              SLICE_R23C82C                        CLKTOQWD_DEL       0.000                  1.132  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.wdo2
                                                                                   NET DELAY          0.000                  1.132  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.dpram_inst_1/DI0->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.dpram_inst_1/DO0
                                              SLICE_R23C82B                        QWDTOF0_DEL        0.552                  1.684  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_rddata[2]
                                                                                   NET DELAY          0.000                  1.684  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i3.ff_inst/DF
                                                                                   ENDPOINT           0.000                  1.684  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i3.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2868/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.000,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":1.994,
            "delay":1.994
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":1.994,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.153,
            "delay":-1.841
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.042,
            "delay":1.889
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.042,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
                                                                                   CONSTRAINT         0.000                  0.000  1
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY      0.000                  0.000  4
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY          1.994                  1.994  4
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                        0.000                  1.994  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                       -1.841                  0.153  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY          1.889                  2.042  1922
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i3.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i4.ff_inst/CLK}
                                                                                   CLOCK PIN          0.000                  2.042  1
                                                                                   Uncertainty        0.000                  2.042
                                                                                   Common Path Skew   0.000                  2.042
                                                                                   Hold time          0.114                  2.156
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    Required Time                                                                                                           -2.156
    Arrival Time                                                                                                             1.683
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    Path Slack  (Failed)                                                                                                    -0.472

    ++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.ramw_inst/WDO0  (SLICE_R23C82C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i1.ff_inst/DF  (SLICE_R23C82A)
    Source Clock     : sclk_o (R)
    Destination Clock: clk_w (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : 0.910 ns
    Hold Constraint  : 0.000 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -0.472 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0.SLICE_2866/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.000,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.262,
            "delay":0.262
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.502,
            "delay":0.240
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.502,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-1.611,
            "delay":-2.113
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.096,
            "delay":0.515
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.096,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-0.947,
            "delay":0.149
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.505,
            "delay":0.442
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.131,
            "delay":1.637
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.131,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    pll_refclk_i                              eval_top                             CLOCK LATENCY      0.000                  0.000  1
    pll_refclk_i                                                                   NET DELAY          0.000                  0.000  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL           0.262                  0.262  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY          0.240                  0.502  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                        0.000                  0.502  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                       -2.113                 -1.611  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY          0.515                 -1.096  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL        0.000                 -1.096  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY          0.149                 -0.947  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL      0.442                 -0.505  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY          1.637                  1.131  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.ramw_inst/WCK
                                                                                   CLOCK PIN          0.000                  1.131  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.ramw_inst/WDO0",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0.SLICE_2866/WDO0"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i1.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2867/DI0"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0.SLICE_2866/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.ramw_inst/WDO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0.SLICE_2866/WDO0"
            },
            "arrive":1.132,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.wdo0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0.wdo0"
            },
            "arrive":1.132,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.dpram_inst_0/DI0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2867/WDI0"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.dpram_inst_0/DO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2867/F0"
            },
            "arrive":1.684,
            "delay":0.552
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_rddata[0]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_rddata[0]"
            },
            "arrive":1.684,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.684,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.ramw_inst/WDO0
                                              SLICE_R23C82C                        CLKTOQWD_DEL       0.000                  1.132  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.wdo0
                                                                                   NET DELAY          0.000                  1.132  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.dpram_inst_0/DI0->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0.dpram_inst_0/DO0
                                              SLICE_R23C82A                        QWDTOF0_DEL        0.552                  1.684  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_rddata[0]
                                                                                   NET DELAY          0.000                  1.684  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i1.ff_inst/DF
                                                                                   ENDPOINT           0.000                  1.684  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i1.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2867/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.000,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":1.994,
            "delay":1.994
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":1.994,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.153,
            "delay":-1.841
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.042,
            "delay":1.889
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.042,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
                                                                                   CONSTRAINT         0.000                  0.000  1
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY      0.000                  0.000  4
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY          1.994                  1.994  4
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                        0.000                  1.994  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                       -1.841                  0.153  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY          1.889                  2.042  1922
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i1.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i2.ff_inst/CLK}
                                                                                   CLOCK PIN          0.000                  2.042  1
                                                                                   Uncertainty        0.000                  2.042
                                                                                   Common Path Skew   0.000                  2.042
                                                                                   Hold time          0.114                  2.156
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    Required Time                                                                                                           -2.156
    Arrival Time                                                                                                             1.683
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    Path Slack  (Failed)                                                                                                    -0.472

    ++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.ramw_inst/WDO2  (SLICE_R23C83C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i7.ff_inst/DF  (SLICE_R23C83B)
    Source Clock     : sclk_o (R)
    Destination Clock: clk_w (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : 0.910 ns
    Hold Constraint  : 0.000 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -0.472 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_6.SLICE_2863/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.000,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.262,
            "delay":0.262
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.502,
            "delay":0.240
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.502,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-1.611,
            "delay":-2.113
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.096,
            "delay":0.515
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.096,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-0.947,
            "delay":0.149
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.505,
            "delay":0.442
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.131,
            "delay":1.637
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.131,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    pll_refclk_i                              eval_top                             CLOCK LATENCY      0.000                  0.000  1
    pll_refclk_i                                                                   NET DELAY          0.000                  0.000  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL           0.262                  0.262  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY          0.240                  0.502  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                        0.000                  0.502  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                       -2.113                 -1.611  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY          0.515                 -1.096  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL        0.000                 -1.096  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY          0.149                 -0.947  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL      0.442                 -0.505  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY          1.637                  1.131  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.ramw_inst/WCK
                                                                                   CLOCK PIN          0.000                  1.131  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.ramw_inst/WDO2",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_6.SLICE_2863/WDO2"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i7.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2865/DI0"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_6.SLICE_2863/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.ramw_inst/WDO2",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_6.SLICE_2863/WDO2"
            },
            "arrive":1.132,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.wdo2",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_6.wdo2"
            },
            "arrive":1.132,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.dpram_inst_1/DI0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2865/WDI0"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.dpram_inst_1/DO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2865/F0"
            },
            "arrive":1.684,
            "delay":0.552
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_rddata[6]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_rddata[6]"
            },
            "arrive":1.684,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.684,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.ramw_inst/WDO2
                                              SLICE_R23C83C                        CLKTOQWD_DEL       0.000                  1.132  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.wdo2
                                                                                   NET DELAY          0.000                  1.132  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.dpram_inst_1/DI0->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.dpram_inst_1/DO0
                                              SLICE_R23C83B                        QWDTOF0_DEL        0.552                  1.684  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_rddata[6]
                                                                                   NET DELAY          0.000                  1.684  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i7.ff_inst/DF
                                                                                   ENDPOINT           0.000                  1.684  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i7.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2865/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.000,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":1.994,
            "delay":1.994
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":1.994,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.153,
            "delay":-1.841
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.042,
            "delay":1.889
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.042,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
                                                                                   CONSTRAINT         0.000                  0.000  1
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY      0.000                  0.000  4
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY          1.994                  1.994  4
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                        0.000                  1.994  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                       -1.841                  0.153  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY          1.889                  2.042  1922
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i7.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i8.ff_inst/CLK}
                                                                                   CLOCK PIN          0.000                  2.042  1
                                                                                   Uncertainty        0.000                  2.042
                                                                                   Common Path Skew   0.000                  2.042
                                                                                   Hold time          0.114                  2.156
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    Required Time                                                                                                           -2.156
    Arrival Time                                                                                                             1.683
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    Path Slack  (Failed)                                                                                                    -0.472

    ++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Path Begin       : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.ramw_inst/WDO0  (SLICE_R23C83C)
    Path End         : u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i5.ff_inst/DF  (SLICE_R23C83A)
    Source Clock     : sclk_o (R)
    Destination Clock: clk_w (R)
    Logic Level      : 2
    Delay Ratio      : 0.0% (route), 100.0% (logic)
    Clock Skew       : 0.910 ns
    Hold Constraint  : 0.000 ns
    Common Path Skew : 0.000 ns
    Path Slack       : -0.472 ns  (Failed)

    Source Clock Path

    {
        "path_begin":
        {
            "type":"port",
            "log_name":"pll_refclk_i",
            "phy_name":"pll_refclk_i"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.ramw_inst/WCK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_6.SLICE_2863/CLK"
        },
        "path_sections":[
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"pll_refclk_i",
                "phy_name":"pll_refclk_i"
            },
            "arrive":0.000,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/B",
                "phy_name":"pll_refclk_i_pad.bb_inst/IOPAD"
            },
            "pin1":
            {
                "log_name":"pll_refclk_i_pad.bb_inst/O",
                "phy_name":"pll_refclk_i_pad.bb_inst/PADDI"
            },
            "arrive":0.262,
            "delay":0.262
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c",
                "phy_name":"pll_refclk_i_c"
            },
            "arrive":0.502,
            "delay":0.240
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":0.502,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
            },
            "arrive":-1.611,
            "delay":-2.113
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w"
            },
            "arrive":-1.096,
            "delay":0.515
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT"
            },
            "arrive":-1.096,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
            },
            "arrive":-0.947,
            "delay":0.149
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/ECLKIN"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT"
            },
            "arrive":-0.505,
            "delay":0.442
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o",
                "phy_name":"sclk_o"
            },
            "arrive":1.131,
            "delay":1.637
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.131,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    pll_refclk_i                              eval_top                             CLOCK LATENCY      0.000                  0.000  1
    pll_refclk_i                                                                   NET DELAY          0.000                  0.000  1
    pll_refclk_i_pad.bb_inst/B->pll_refclk_i_pad.bb_inst/O
                                              DIFFIO18A_CORE_T2                    PADI_DEL           0.262                  0.262  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/pll_refclk_i_c
                                                                                   NET DELAY          0.240                  0.502  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
                                              PLL_CORE_PLL_LLC                                        0.000                  0.502  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_LLC                                       -2.113                 -1.611  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/eclk_w
                                                                                   NET DELAY          0.515                 -1.096  1
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst/ECLKOUT
                                              ECLKSYNC_CORE_ECLKSYNC_CORE_R73C74B  CLK2OUT_DEL        0.000                 -1.096  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/CA_GRP_ENA.u_ca_grp/eclkout_w
                                                                                   NET DELAY          0.149                 -0.947  33
    u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/ECLKIN->u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst/DIVOUT
                                              ECLKDIV_CORE_ECLKDIV_CORE_R73C74B    CLKDIVOUT_DEL      0.442                 -0.505  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/sclk_o
                                                                                   NET DELAY          1.637                  1.131  6014
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.ramw_inst/WCK
                                                                                   CLOCK PIN          0.000                  1.131  1

    Data Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.ramw_inst/WDO0",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_6.SLICE_2863/WDO0"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i5.ff_inst/DF",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2864/DI0"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.ramw_inst/WCK",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_6.SLICE_2863/CLK"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.ramw_inst/WDO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_6.SLICE_2863/WDO0"
            },
            "arrive":1.132,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.wdo0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_wraddr_0__I_0_6.wdo0"
            },
            "arrive":1.132,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.dpram_inst_0/DI0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2864/WDI0"
            },
            "pin1":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.dpram_inst_0/DO0",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2864/F0"
            },
            "arrive":1.684,
            "delay":0.552
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_rddata[4]",
                "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.dpram_rddata[4]"
            },
            "arrive":1.684,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":1.684,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.ramw_inst/WCK->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.ramw_inst/WDO0
                                              SLICE_R23C83C                        CLKTOQWD_DEL       0.000                  1.132  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.wdo0
                                                                                   NET DELAY          0.000                  1.132  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.dpram_inst_0/DI0->u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_wraddr_0__I_0_6.dpram_inst_0/DO0
                                              SLICE_R23C83A                        QWDTOF0_DEL        0.552                  1.684  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/dpram_rddata[4]
                                                                                   NET DELAY          0.000                  1.684  1
    u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i5.ff_inst/DF
                                                                                   ENDPOINT           0.000                  1.684  1

    Destination Clock Path

    {
        "path_begin":
        {
            "type":"pin",
            "log_name":"osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst/HFCLKOUT",
            "phy_name":"osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT"
        },
        "path_end":
        {
            "type":"pin",
            "log_name":"u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i5.ff_inst/CLK",
            "phy_name":"u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.u_ctrl_dpram.lscc_distributed_dpram_inst.SLICE_2864/CLK"
        },
        "path_sections":[
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":0.000,
            "delay":0.000
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90",
                "phy_name":"osc_clk_90"
            },
            "arrive":1.994,
            "delay":1.994
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":1.994,
            "delay":0.000
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
            },
            "pin1":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
                "phy_name":"ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
            },
            "arrive":0.153,
            "delay":-1.841
        },
        {
            "type":"net_delay",
            "net":
            {
                "log_name":"ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w",
                "phy_name":"clk_w"
            },
            "arrive":2.042,
            "delay":1.889
        },
        {
            "type":"site_delay",
            "pin0":
            {
                "log_name":"",
                "phy_name":""
            },
            "pin1":
            {
                "log_name":"",
                "phy_name":""
            },
            "arrive":2.042,
            "delay":0.000
        }
        ]
    }

    Name                                      Cell/Site Name                       Delay Name        Incr    Arrival/Required Time  Fanout
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
                                                                                   CONSTRAINT         0.000                  0.000  1
    osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT
                                              OSC_CORE_OSC_CORE_R1C137             CLOCK LATENCY      0.000                  0.000  4
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/osc_clk_90
                                                                                   NET DELAY          1.994                  1.994  4
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
                                              PLL_CORE_PLL_ULC                                        0.000                  1.994  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
                                              PLL_CORE_PLL_ULC                                       -1.841                  0.153  1922
    ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/clk_w
                                                                                   NET DELAY          1.889                  2.042  1922
    {u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i5.ff_inst/CLK   u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/i11407__2__i6.ff_inst/CLK}
                                                                                   CLOCK PIN          0.000                  2.042  1
                                                                                   Uncertainty        0.000                  2.042
                                                                                   Common Path Skew   0.000                  2.042
                                                                                   Hold time          0.114                  2.156
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    Required Time                                                                                                           -2.156
    Arrival Time                                                                                                             1.683
    ----------------------------------------  -----------------------------------  ----------------  ------  ---------------------  ------
    Path Slack  (Failed)                                                                                                    -0.472

    +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
                        End of Detailed Report for timing paths
    +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    ##########################################################