
/*******************************************************************************
    Verilog netlist generated by IPGEN Lattice Propel (64-bit) 0.0.11.31.0
    Soft IP Version: 1.0.0
    Thu Jun 11 13:34:26 2020
*******************************************************************************/
/*******************************************************************************
    Wrapper Module generated per user settings.
*******************************************************************************/
module ahbl0 (ahbl_hclk_i, 
        ahbl_hresetn_i, 
        ahbl_m01_hready_mstr_i, 
        ahbl_m01_hresp_mstr_i, 
        ahbl_m01_hrdata_mstr_i, 
        ahbl_m01_hsel_mstr_o, 
        ahbl_m01_haddr_mstr_o, 
        ahbl_m01_hburst_mstr_o, 
        ahbl_m01_hsize_mstr_o, 
        ahbl_m01_hmastlock_mstr_o, 
        ahbl_m01_hprot_mstr_o, 
        ahbl_m01_htrans_mstr_o, 
        ahbl_m01_hwdata_mstr_o, 
        ahbl_m01_hwrite_mstr_o, 
        ahbl_m01_hready_mstr_o, 
        ahbl_s00_hsel_slv_i, 
        ahbl_s00_haddr_slv_i, 
        ahbl_s00_hburst_slv_i, 
        ahbl_s00_hsize_slv_i, 
        ahbl_s00_hmastlock_slv_i, 
        ahbl_s00_hprot_slv_i, 
        ahbl_s00_htrans_slv_i, 
        ahbl_s00_hwdata_slv_i, 
        ahbl_s00_hwrite_slv_i, 
        ahbl_s00_hready_slv_i, 
        ahbl_s00_hreadyout_slv_o, 
        ahbl_s00_hresp_slv_o, 
        ahbl_s00_hrdata_slv_o, 
        ahbl_m00_hready_mstr_i, 
        ahbl_m00_hresp_mstr_i, 
        ahbl_m00_hrdata_mstr_i, 
        ahbl_m00_hsel_mstr_o, 
        ahbl_m00_haddr_mstr_o, 
        ahbl_m00_hburst_mstr_o, 
        ahbl_m00_hsize_mstr_o, 
        ahbl_m00_hmastlock_mstr_o, 
        ahbl_m00_hprot_mstr_o, 
        ahbl_m00_htrans_mstr_o, 
        ahbl_m00_hwdata_mstr_o, 
        ahbl_m00_hwrite_mstr_o, 
        ahbl_m00_hready_mstr_o) ;
    input ahbl_hclk_i ; 
    input ahbl_hresetn_i ; 
    input [0:0] ahbl_m01_hready_mstr_i ; 
    input [0:0] ahbl_m01_hresp_mstr_i ; 
    input [31:0] ahbl_m01_hrdata_mstr_i ; 
    output [0:0] ahbl_m01_hsel_mstr_o ; 
    output [31:0] ahbl_m01_haddr_mstr_o ; 
    output [2:0] ahbl_m01_hburst_mstr_o ; 
    output [2:0] ahbl_m01_hsize_mstr_o ; 
    output [0:0] ahbl_m01_hmastlock_mstr_o ; 
    output [3:0] ahbl_m01_hprot_mstr_o ; 
    output [1:0] ahbl_m01_htrans_mstr_o ; 
    output [31:0] ahbl_m01_hwdata_mstr_o ; 
    output [0:0] ahbl_m01_hwrite_mstr_o ; 
    output [0:0] ahbl_m01_hready_mstr_o ; 
    input [0:0] ahbl_s00_hsel_slv_i ; 
    input [31:0] ahbl_s00_haddr_slv_i ; 
    input [2:0] ahbl_s00_hburst_slv_i ; 
    input [2:0] ahbl_s00_hsize_slv_i ; 
    input [0:0] ahbl_s00_hmastlock_slv_i ; 
    input [3:0] ahbl_s00_hprot_slv_i ; 
    input [1:0] ahbl_s00_htrans_slv_i ; 
    input [31:0] ahbl_s00_hwdata_slv_i ; 
    input [0:0] ahbl_s00_hwrite_slv_i ; 
    input [0:0] ahbl_s00_hready_slv_i ; 
    output [0:0] ahbl_s00_hreadyout_slv_o ; 
    output [0:0] ahbl_s00_hresp_slv_o ; 
    output [31:0] ahbl_s00_hrdata_slv_o ; 
    input [0:0] ahbl_m00_hready_mstr_i ; 
    input [0:0] ahbl_m00_hresp_mstr_i ; 
    input [31:0] ahbl_m00_hrdata_mstr_i ; 
    output [0:0] ahbl_m00_hsel_mstr_o ; 
    output [31:0] ahbl_m00_haddr_mstr_o ; 
    output [2:0] ahbl_m00_hburst_mstr_o ; 
    output [2:0] ahbl_m00_hsize_mstr_o ; 
    output [0:0] ahbl_m00_hmastlock_mstr_o ; 
    output [3:0] ahbl_m00_hprot_mstr_o ; 
    output [1:0] ahbl_m00_htrans_mstr_o ; 
    output [31:0] ahbl_m00_hwdata_mstr_o ; 
    output [0:0] ahbl_m00_hwrite_mstr_o ; 
    output [0:0] ahbl_m00_hready_mstr_o ; 
    parameter M_ADDR_WIDTH = 32 ; 
    parameter FULL_DECODE_EN = 1 ; 
    parameter S0_FRAGMENT_EN = 1 ; 
    parameter S0_BASE_ADDR = 32'h00000000 ; 
    parameter S0_ADDR_RANGE = 32'h00000400 ; 
    parameter S1_FRAGMENT_EN = 1 ; 
    parameter S1_BASE_ADDR = 32'h00002000 ; 
    parameter S1_ADDR_RANGE = 32'h00000400 ; 
    ahbl0_ipgen_lscc_ahbl_interconnect #(.TOTAL_MASTER_CNT(1),
            .TOTAL_SLAVE_CNT(2),
            .M_ADDR_WIDTH(M_ADDR_WIDTH),
            .FULL_DECODE_EN(FULL_DECODE_EN),
            .DATA_WIDTH(32),
            .OUTREG_EN(0),
            .FAMILY("je5d00"),
            .S0_FRAGMENT_EN(S0_FRAGMENT_EN),
            .S0_BASE_ADDR(S0_BASE_ADDR),
            .S0_ADDR_RANGE(S0_ADDR_RANGE),
            .S1_FRAGMENT_EN(S1_FRAGMENT_EN),
            .S1_BASE_ADDR(S1_BASE_ADDR),
            .S1_ADDR_RANGE(S1_ADDR_RANGE),
            .S2_FRAGMENT_EN(1),
            .S2_BASE_ADDR(32'h00004000),
            .S2_ADDR_RANGE(32'h00000400),
            .S3_FRAGMENT_EN(1),
            .S3_BASE_ADDR(32'h00006000),
            .S3_ADDR_RANGE(32'h00000400),
            .S4_FRAGMENT_EN(1),
            .S4_BASE_ADDR(32'h00008000),
            .S4_ADDR_RANGE(32'h00000400),
            .S5_FRAGMENT_EN(1),
            .S5_BASE_ADDR(32'h0000a000),
            .S5_ADDR_RANGE(32'h00000400),
            .S6_FRAGMENT_EN(1),
            .S6_BASE_ADDR(32'h0000c000),
            .S6_ADDR_RANGE(32'h00000400),
            .S7_FRAGMENT_EN(1),
            .S7_BASE_ADDR(32'h0000e000),
            .S7_ADDR_RANGE(32'h00000400),
            .S8_FRAGMENT_EN(1),
            .S8_BASE_ADDR(32'h00010000),
            .S8_ADDR_RANGE(32'h00000400),
            .S9_FRAGMENT_EN(1),
            .S9_BASE_ADDR(32'h00012000),
            .S9_ADDR_RANGE(32'h00000400),
            .S10_FRAGMENT_EN(1),
            .S10_BASE_ADDR(32'h00014000),
            .S10_ADDR_RANGE(32'h00000400),
            .S11_FRAGMENT_EN(1),
            .S11_BASE_ADDR(32'h00016000),
            .S11_ADDR_RANGE(32'h00000400),
            .S12_FRAGMENT_EN(1),
            .S12_BASE_ADDR(32'h00018000),
            .S12_ADDR_RANGE(32'h00000400),
            .S13_FRAGMENT_EN(1),
            .S13_BASE_ADDR(32'h0001a000),
            .S13_ADDR_RANGE(32'h00000400),
            .S14_FRAGMENT_EN(1),
            .S14_BASE_ADDR(32'h0001c000),
            .S14_ADDR_RANGE(32'h00000400),
            .S15_FRAGMENT_EN(1),
            .S15_BASE_ADDR(32'h0001e000),
            .S15_ADDR_RANGE(32'h00000400),
            .S16_FRAGMENT_EN(1),
            .S16_BASE_ADDR(32'h00020000),
            .S16_ADDR_RANGE(32'h00000400),
            .S17_FRAGMENT_EN(1),
            .S17_BASE_ADDR(32'h00022000),
            .S17_ADDR_RANGE(32'h00000400),
            .S18_FRAGMENT_EN(1),
            .S18_BASE_ADDR(32'h00024000),
            .S18_ADDR_RANGE(32'h00000400),
            .S19_FRAGMENT_EN(1),
            .S19_BASE_ADDR(32'h00026000),
            .S19_ADDR_RANGE(32'h00000400),
            .S20_FRAGMENT_EN(1),
            .S20_BASE_ADDR(32'h00028000),
            .S20_ADDR_RANGE(32'h00000400),
            .S21_FRAGMENT_EN(1),
            .S21_BASE_ADDR(32'h0002a000),
            .S21_ADDR_RANGE(32'h00000400),
            .S22_FRAGMENT_EN(1),
            .S22_BASE_ADDR(32'h0002c000),
            .S22_ADDR_RANGE(32'h00000400),
            .S23_FRAGMENT_EN(1),
            .S23_BASE_ADDR(32'h0002e000),
            .S23_ADDR_RANGE(32'h00000400),
            .S24_FRAGMENT_EN(1),
            .S24_BASE_ADDR(32'h00030000),
            .S24_ADDR_RANGE(32'h00000400),
            .S25_FRAGMENT_EN(1),
            .S25_BASE_ADDR(32'h00032000),
            .S25_ADDR_RANGE(32'h00000400),
            .S26_FRAGMENT_EN(1),
            .S26_BASE_ADDR(32'h00034000),
            .S26_ADDR_RANGE(32'h00000400),
            .S27_FRAGMENT_EN(1),
            .S27_BASE_ADDR(32'h00036000),
            .S27_ADDR_RANGE(32'h00000400),
            .S28_FRAGMENT_EN(1),
            .S28_BASE_ADDR(32'h00038000),
            .S28_ADDR_RANGE(32'h00000400),
            .S29_FRAGMENT_EN(1),
            .S29_BASE_ADDR(32'h0003a000),
            .S29_ADDR_RANGE(32'h00000400),
            .S30_FRAGMENT_EN(1),
            .S30_BASE_ADDR(32'h0003c000),
            .S30_ADDR_RANGE(32'h00000400),
            .S31_FRAGMENT_EN(1),
            .S31_BASE_ADDR(32'h0003e000),
            .S31_ADDR_RANGE(32'h00000400),
            .S0_ARBITER_SCHEME(3'd0),
            .S0_M_PRIO_IDX(1'd1),
            .S1_ARBITER_SCHEME(3'd0),
            .S1_M_PRIO_IDX(1'd1),
            .S2_ARBITER_SCHEME(3'd0),
            .S2_M_PRIO_IDX(1'd1),
            .S3_ARBITER_SCHEME(3'd0),
            .S3_M_PRIO_IDX(1'd1),
            .S4_ARBITER_SCHEME(3'd0),
            .S4_M_PRIO_IDX(1'd1),
            .S5_ARBITER_SCHEME(3'd0),
            .S5_M_PRIO_IDX(1'd1),
            .S6_ARBITER_SCHEME(3'd0),
            .S6_M_PRIO_IDX(1'd1),
            .S7_ARBITER_SCHEME(3'd0),
            .S7_M_PRIO_IDX(1'd1),
            .S8_ARBITER_SCHEME(3'd0),
            .S8_M_PRIO_IDX(1'd1),
            .S9_ARBITER_SCHEME(3'd0),
            .S9_M_PRIO_IDX(1'd1),
            .S10_ARBITER_SCHEME(3'd0),
            .S10_M_PRIO_IDX(1'd1),
            .S11_ARBITER_SCHEME(3'd0),
            .S11_M_PRIO_IDX(1'd1),
            .S12_ARBITER_SCHEME(3'd0),
            .S12_M_PRIO_IDX(1'd1),
            .S13_ARBITER_SCHEME(3'd0),
            .S13_M_PRIO_IDX(1'd1),
            .S14_ARBITER_SCHEME(3'd0),
            .S14_M_PRIO_IDX(1'd1),
            .S15_ARBITER_SCHEME(3'd0),
            .S15_M_PRIO_IDX(1'd1),
            .S16_ARBITER_SCHEME(3'd0),
            .S16_M_PRIO_IDX(1'd1),
            .S17_ARBITER_SCHEME(3'd0),
            .S17_M_PRIO_IDX(1'd1),
            .S18_ARBITER_SCHEME(3'd0),
            .S18_M_PRIO_IDX(1'd1),
            .S19_ARBITER_SCHEME(3'd0),
            .S19_M_PRIO_IDX(1'd1),
            .S20_ARBITER_SCHEME(3'd0),
            .S20_M_PRIO_IDX(1'd1),
            .S21_ARBITER_SCHEME(3'd0),
            .S21_M_PRIO_IDX(1'd1),
            .S22_ARBITER_SCHEME(3'd0),
            .S22_M_PRIO_IDX(1'd1),
            .S23_ARBITER_SCHEME(3'd0),
            .S23_M_PRIO_IDX(1'd1),
            .S24_ARBITER_SCHEME(3'd0),
            .S24_M_PRIO_IDX(1'd1),
            .S25_ARBITER_SCHEME(3'd0),
            .S25_M_PRIO_IDX(1'd1),
            .S26_ARBITER_SCHEME(3'd0),
            .S26_M_PRIO_IDX(1'd1),
            .S27_ARBITER_SCHEME(3'd0),
            .S27_M_PRIO_IDX(1'd1),
            .S28_ARBITER_SCHEME(3'd0),
            .S28_M_PRIO_IDX(1'd1),
            .S29_ARBITER_SCHEME(3'd0),
            .S29_M_PRIO_IDX(1'd1),
            .S30_ARBITER_SCHEME(3'd0),
            .S30_M_PRIO_IDX(1'd1),
            .S31_ARBITER_SCHEME(3'd0),
            .S31_M_PRIO_IDX(1'd1),
            .S0_MAX_BURST_SIZE(0),
            .S1_MAX_BURST_SIZE(0),
            .S2_MAX_BURST_SIZE(0),
            .S3_MAX_BURST_SIZE(0),
            .S4_MAX_BURST_SIZE(0),
            .S5_MAX_BURST_SIZE(0),
            .S6_MAX_BURST_SIZE(0),
            .S7_MAX_BURST_SIZE(0),
            .S8_MAX_BURST_SIZE(0),
            .S9_MAX_BURST_SIZE(0),
            .S10_MAX_BURST_SIZE(0),
            .S11_MAX_BURST_SIZE(0),
            .S12_MAX_BURST_SIZE(0),
            .S13_MAX_BURST_SIZE(0),
            .S14_MAX_BURST_SIZE(0),
            .S15_MAX_BURST_SIZE(0),
            .S16_MAX_BURST_SIZE(0),
            .S17_MAX_BURST_SIZE(0),
            .S18_MAX_BURST_SIZE(0),
            .S19_MAX_BURST_SIZE(0),
            .S20_MAX_BURST_SIZE(0),
            .S21_MAX_BURST_SIZE(0),
            .S22_MAX_BURST_SIZE(0),
            .S23_MAX_BURST_SIZE(0),
            .S24_MAX_BURST_SIZE(0),
            .S25_MAX_BURST_SIZE(0),
            .S26_MAX_BURST_SIZE(0),
            .S27_MAX_BURST_SIZE(0),
            .S28_MAX_BURST_SIZE(0),
            .S29_MAX_BURST_SIZE(0),
            .S30_MAX_BURST_SIZE(0),
            .S31_MAX_BURST_SIZE(0)) lscc_ahbl_interconnect_inst (.ahbl_hclk_i(ahbl_hclk_i), 
                .ahbl_hresetn_i(ahbl_hresetn_i), 
                .ahbl_hsel_slv_i({ahbl_s00_hsel_slv_i[0]}), 
                .ahbl_haddr_slv_i({ahbl_s00_haddr_slv_i[31:0]}), 
                .ahbl_hburst_slv_i({ahbl_s00_hburst_slv_i[2:0]}), 
                .ahbl_hsize_slv_i({ahbl_s00_hsize_slv_i[2:0]}), 
                .ahbl_hmastlock_slv_i({ahbl_s00_hmastlock_slv_i[0]}), 
                .ahbl_hprot_slv_i({ahbl_s00_hprot_slv_i[3:0]}), 
                .ahbl_htrans_slv_i({ahbl_s00_htrans_slv_i[1:0]}), 
                .ahbl_hwdata_slv_i({ahbl_s00_hwdata_slv_i[31:0]}), 
                .ahbl_hwrite_slv_i({ahbl_s00_hwrite_slv_i[0]}), 
                .ahbl_hready_slv_i({ahbl_s00_hready_slv_i[0]}), 
                .ahbl_hreadyout_slv_o({ahbl_s00_hreadyout_slv_o[0]}), 
                .ahbl_hresp_slv_o({ahbl_s00_hresp_slv_o[0]}), 
                .ahbl_hrdata_slv_o({ahbl_s00_hrdata_slv_o[31:0]}), 
                .ahbl_hready_mstr_i({ahbl_m01_hready_mstr_i[0],
                    ahbl_m00_hready_mstr_i[0]}), 
                .ahbl_hresp_mstr_i({ahbl_m01_hresp_mstr_i[0],
                    ahbl_m00_hresp_mstr_i[0]}), 
                .ahbl_hrdata_mstr_i({ahbl_m01_hrdata_mstr_i[31:0],
                    ahbl_m00_hrdata_mstr_i[31:0]}), 
                .ahbl_hsel_mstr_o({ahbl_m01_hsel_mstr_o[0],
                    ahbl_m00_hsel_mstr_o[0]}), 
                .ahbl_haddr_mstr_o({ahbl_m01_haddr_mstr_o[31:0],
                    ahbl_m00_haddr_mstr_o[31:0]}), 
                .ahbl_hburst_mstr_o({ahbl_m01_hburst_mstr_o[2:0],
                    ahbl_m00_hburst_mstr_o[2:0]}), 
                .ahbl_hsize_mstr_o({ahbl_m01_hsize_mstr_o[2:0],
                    ahbl_m00_hsize_mstr_o[2:0]}), 
                .ahbl_hmastlock_mstr_o({ahbl_m01_hmastlock_mstr_o[0],
                    ahbl_m00_hmastlock_mstr_o[0]}), 
                .ahbl_hprot_mstr_o({ahbl_m01_hprot_mstr_o[3:0],
                    ahbl_m00_hprot_mstr_o[3:0]}), 
                .ahbl_htrans_mstr_o({ahbl_m01_htrans_mstr_o[1:0],
                    ahbl_m00_htrans_mstr_o[1:0]}), 
                .ahbl_hwdata_mstr_o({ahbl_m01_hwdata_mstr_o[31:0],
                    ahbl_m00_hwdata_mstr_o[31:0]}), 
                .ahbl_hwrite_mstr_o({ahbl_m01_hwrite_mstr_o[0],
                    ahbl_m00_hwrite_mstr_o[0]}), 
                .ahbl_hready_mstr_o({ahbl_m01_hready_mstr_o[0],
                    ahbl_m00_hready_mstr_o[0]})) ; 
endmodule



`timescale 1ns/1ps

/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2022 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_arbiter.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
module ahbl0_ipgen_lscc_ahbl_arbiter #(parameter TOTAL_MASTER_CNT = 8, 
        parameter M_PRIO_WIDTH = clog2(TOTAL_MASTER_CNT), 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter DATA_WIDTH = 32, 
        parameter [2:0] ARBITER_SCHEME = 3'b0, 
        parameter [8:0] MAX_BURST_SIZE = 9'd0) (
    // -----------------------------------------------------------------------------
    // Module Parameters
    // -----------------------------------------------------------------------------
    // ------------------------------------------------------------------------------
    // Input/Output Ports
    // ------------------------------------------------------------------------------
    input ahbl_hclk_i, 
    input ahbl_hresetn_i, 
    input ahbl_arb_en_i, 
    input ahbl_ack_i, 
    input [(TOTAL_MASTER_CNT - 1):0] ahbl_req_i, 
    input ahbl_adv_cnt_i, 
    output reg [(TOTAL_MASTER_CNT - 1):0] ahbl_gnt_o, 
    output reg [(TOTAL_MASTER_CNT - 1):0] ahbl_gnt_nxt_o, 
    output reg ahbl_max_reached_o) ;
    // ------------------------------------------------------------------------------
    // Local Parameters
    // ------------------------------------------------------------------------------
    localparam M = TOTAL_MASTER_CNT ; 
    localparam PW = M_PRIO_WIDTH ; 
    localparam CNT_STEP = 9'h01 ; 
    localparam CNT_ZERO = 9'h00 ; 
    localparam CNT_WIDTH = 9 ; 
    localparam ST_WIDTH = 2 ; 
    localparam ST_IDLE = 2'b01 ; 
    localparam ST_ACTIVE = 2'b10 ; 
    // ------------------------------------------------------------------------------
    // Generate Variables
    // ------------------------------------------------------------------------------
    genvar i ; 
    // ------------------------------------------------------------------------------
    // Register Declarations
    // ------------------------------------------------------------------------------
    reg arb_en_r ; 
    reg [(CNT_WIDTH - 1):0] run_cnt_r ; 
    // ------------------------------------------------------------------------------
    // Wire Declarations
    // ------------------------------------------------------------------------------
    wire [(M - 1):0] req_in ; 
    //wire [M-1:0]                            req_mask;
    wire [((M * PW) - 1):0] prio_idx = M_PRIO_IDX ; 
    wire [(CNT_WIDTH - 1):0] max_burst = MAX_BURST_SIZE ; 
    // ------------------------------------------------------------------------------
    // Generate Blocks
    // ------------------------------------------------------------------------------
    generate
        if ((MAX_BURST_SIZE == 0)) 
            begin : dis_max_burst
                always
                    @(*)
                    begin
                        ahbl_max_reached_o = 0 ;
                    end
            end
        else
            begin : en_max_burst
                //------------------------------------------------------------------------------
                // Sequential Blocks
                //------------------------------------------------------------------------------
                integer k ; 
                always
                    @(posedge ahbl_hclk_i or 
                        negedge ahbl_hresetn_i)
                    begin
                        if ((~ahbl_hresetn_i)) 
                            begin
                                run_cnt_r <=  MAX_BURST_SIZE ;
                                arb_en_r <=  1'b0 ;
                                ahbl_max_reached_o <=  1'b0 ;
                            end
                        else
                            begin
                                arb_en_r <=  ahbl_arb_en_i ;
                                if (ahbl_ack_i) 
                                    run_cnt_r <=  MAX_BURST_SIZE ;
                                else
                                    if (arb_en_r) 
                                        run_cnt_r <=  (MAX_BURST_SIZE - CNT_STEP) ;
                                    else
                                        begin
                                            run_cnt_r <=  ((ahbl_adv_cnt_i && (run_cnt_r == CNT_ZERO)) ? (run_cnt_r - CNT_STEP) : run_cnt_r) ;
                                        end
                                if (((run_cnt_r == CNT_ZERO) || ((run_cnt_r == CNT_STEP) && ahbl_adv_cnt_i))) 
                                    ahbl_max_reached_o <=  1'b1 ;
                                else
                                    ahbl_max_reached_o <=  1'b0 ;
                            end
                    end
            end
    endgenerate
    // ------------------------------------------------------------------------------
    // Round-Robin Arbitration Scheme
    // ------------------------------------------------------------------------------
    generate
        if ((ARBITER_SCHEME == 3'b0)) 
            begin : round_robin
                wire [(TOTAL_MASTER_CNT - 1):0] done_w ; 
                wire [(TOTAL_MASTER_CNT - 1):0] gnt_w ; 
                wire [(TOTAL_MASTER_CNT - 1):0] gnt_nxt_w ; 
                assign done_w = ((ahbl_arb_en_i || ahbl_ack_i) ? gnt_w : {TOTAL_MASTER_CNT{1'b0}}) ; 
                always
                    @(*)
                    begin
                        ahbl_gnt_o = gnt_w ;
                        ahbl_gnt_nxt_o = gnt_nxt_w ;
                    end
                ahbl0_ipgen_lscc_ahbl_fair_arb #(.NUM_REQ(TOTAL_MASTER_CNT),
                        .ONEHOTPRIO(1'b1)) u_fair_arb (// number of requestor
                        .clk(ahbl_hclk_i), 
                            .rst_n(ahbl_hresetn_i), 
                            .req(ahbl_req_i), 
                            .done(done_w), 
                            .gnt_nxt(gnt_nxt_w), 
                            .gnt(gnt_w)) ; 
            end
    endgenerate
    // ------------------------------------------------------------------------------
    // Fixed Priority Arbitration Scheme
    // ------------------------------------------------------------------------------
    generate
        if ((ARBITER_SCHEME == 3'b1)) 
            begin : fixed_prio
                // --------------------------------------------------------------------------
                // Wire Declarations
                // --------------------------------------------------------------------------
                wire [(M - 1):0] gnt ; 
                wire valid = (|req_in) ; 
                // --------------------------------------------------------------------------
                // Assign Statements
                // --------------------------------------------------------------------------
                for (i = 0;(i < M);i = (i + 1))
                begin : genblk1
                    assign req_in[M_PRIO_IDX[((PW + (PW * i)) - 1):(PW * i)]] = ahbl_req_i[i] ; // && ~req_mask[i];
                end
                always
                    @(*)
                    begin
                        if (ahbl_ack_i) 
                            begin
                                ahbl_gnt_nxt_o = {M{1'b0}} ;
                            end
                        else
                            if (ahbl_arb_en_i) 
                                begin
                                    ahbl_gnt_nxt_o = (valid ? gnt : ahbl_gnt_o) ;
                                end
                            else
                                begin
                                    ahbl_gnt_nxt_o = ahbl_gnt_o ;
                                end
                    end
                // --------------------------------------------------------------------------
                // Sequential Blocks
                // --------------------------------------------------------------------------
                always
                    @(posedge ahbl_hclk_i or 
                        negedge ahbl_hresetn_i)
                    begin
                        if ((~ahbl_hresetn_i)) 
                            begin
                                ahbl_gnt_o <=  {M{1'b0}} ;
                            end
                        else
                            begin
                                ahbl_gnt_o <=  ahbl_gnt_nxt_o ;
                            end
                    end
                // --------------------------------------------------------------------------
                // Submodule Instantiations
                // --------------------------------------------------------------------------
                // -----------------
                // Priority Arbiter
                // -----------------
                ahbl0_ipgen_lscc_ahbl_prio_arb #(.M(M)) u_lscc_ahbl_fp_gnt (//AUTOINSTPARAM*/
                        // Parameters
                        //AUTOINST*/
                        // Outputs
                        .gnt_o(gnt[(M - 1):0]), 
                            // Inputs
                        .req_i(req_in[(M - 1):0])) ; 
            end
    endgenerate
    //------------------------------------------------------------------------------
    // Function Definition
    //------------------------------------------------------------------------------
    function integer clog2( 
        input integer depth )  ; 
        begin
            if ((depth == 0)) 
                clog2 = 1 ;
            else
                for (clog2 = 0 ; (depth > 0) ; clog2 = (clog2 + 1))
                    depth = (depth >> 1) ;
        end
    endfunction

// lscc_ahbl_arbiter
endmodule



`timescale 1ns/1ps
//===============================================================================
// lscc_ahbl_arbiter.v
// Local Variables:
// verilog-library-directories:(".")
// End:
//===============================================================================
// ==============================================================================
// AHB-Lite Priority Arbiter
// ==============================================================================
module ahbl0_ipgen_lscc_ahbl_prio_arb #(parameter M = 32) (
    // -----------------------------------------------------------------------------
    // Module Parameters
    // -----------------------------------------------------------------------------
    // ------------------------------------------------------------------------------
    // Input/Output Ports
    // ------------------------------------------------------------------------------
    input [(M - 1):0] req_i, 
    output reg [(M - 1):0] gnt_o) ;
    // ------------------------------------------------------------------------------
    // Combinatorial Block
    // ------------------------------------------------------------------------------
    always
        @(*)
        begin
            gnt_o = (req_i & (-req_i)) ;
        end
endmodule



`timescale 1ns/1ps
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_arbmux.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
module ahbl0_ipgen_lscc_ahbl_arbmux #(parameter TOTAL_MASTER_CNT = 8, 
        parameter M_ADDR_WIDTH = 32, 
        parameter M_PRIO_WIDTH = clog2(TOTAL_MASTER_CNT), 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter DATA_WIDTH = 32, 
        parameter OUTREG_EN = 0, 
        parameter [2:0] ARBITER_SCHEME = 3'b0, 
        parameter [8:0] MAX_BURST_SIZE = 9'd0) (
    // -----------------------------------------------------------------------------
    // Module Parameters
    // -----------------------------------------------------------------------------
    // ------------------------------------------------------------------------------
    // Input/Output Ports
    // ------------------------------------------------------------------------------
    input ahbl_hclk_i, 
    input ahbl_hresetn_i, 
    // ----------------------------------------
    // AHB-Lite Input Stage
    // ----------------------------------------
    output wire [(TOTAL_MASTER_CNT - 1):0] ahbl_arb_en_slv_o, 
    output wire [(TOTAL_MASTER_CNT - 1):0] ahbl_start_slv_o, 
    output wire [(TOTAL_MASTER_CNT - 1):0] ahbl_grant_slv_o, 
    output wire [(TOTAL_MASTER_CNT - 1):0] ahbl_wait_slv_o, 
    output wire [(TOTAL_MASTER_CNT - 1):0] ahbl_addr_stall_o, 
    // ----------------------------------------
    // AHB-Lite Master Interface (to/from master)
    // ----------------------------------------
    input [(TOTAL_MASTER_CNT - 1):0] ahbl_hsel_slv_i, 
    input [((TOTAL_MASTER_CNT * M_ADDR_WIDTH) - 1):0] ahbl_haddr_slv_i, 
    input [((TOTAL_MASTER_CNT * 3) - 1):0] ahbl_hburst_slv_i, 
    input [((TOTAL_MASTER_CNT * 3) - 1):0] ahbl_hsize_slv_i, 
    input [(TOTAL_MASTER_CNT - 1):0] ahbl_hmastlock_slv_i, 
    input [((TOTAL_MASTER_CNT * 4) - 1):0] ahbl_hprot_slv_i, 
    input [((TOTAL_MASTER_CNT * 2) - 1):0] ahbl_htrans_slv_i, 
    input [((TOTAL_MASTER_CNT * DATA_WIDTH) - 1):0] ahbl_hwdata_slv_i, 
    input [(TOTAL_MASTER_CNT - 1):0] ahbl_hwrite_slv_i, 
    input [(TOTAL_MASTER_CNT - 1):0] ahbl_hready_slv_i, 
    output reg [(TOTAL_MASTER_CNT - 1):0] ahbl_hreadyout_slv_o, 
    output reg [(TOTAL_MASTER_CNT - 1):0] ahbl_hresp_slv_o, 
    output reg [((TOTAL_MASTER_CNT * DATA_WIDTH) - 1):0] ahbl_hrdata_slv_o, 
    // -----------------------------------------
    // AHB-Lite Slave Interface (to/from slave)
    // -----------------------------------------
    output reg ahbl_hsel_mstr_o, 
    output reg [(M_ADDR_WIDTH - 1):0] ahbl_haddr_mstr_o, 
    output reg [2:0] ahbl_hburst_mstr_o, 
    output reg [2:0] ahbl_hsize_mstr_o, 
    output reg ahbl_hmastlock_mstr_o, 
    output reg [3:0] ahbl_hprot_mstr_o, 
    output reg [1:0] ahbl_htrans_mstr_o, 
    output reg [(DATA_WIDTH - 1):0] ahbl_hwdata_mstr_o, 
    output reg ahbl_hwrite_mstr_o, 
    output reg ahbl_hready_mstr_o, 
    input ahbl_hreadyout_mstr_i, 
    input ahbl_hresp_mstr_i, 
    input [(DATA_WIDTH - 1):0] ahbl_hrdata_mstr_i) ;
    // ------------------------------------------------------------------------------
    // Local Parameters
    // ------------------------------------------------------------------------------
    localparam IDLE = 2'b00 ; 
    localparam BUSY = 2'b01 ; 
    localparam NSEQ = 2'b10 ; 
    localparam SEQ = 2'b11 ; 
    localparam ST_WIDTH = 5 ; 
    localparam ST_IDLE = 5'b00001 ; 
    localparam ST_REQ = 5'b00010 ; 
    localparam ST_ACTIVE = 5'b00100 ; 
    localparam ST_ERR0 = 5'b01000 ; 
    localparam ST_ERR1 = 5'b10000 ; 
    localparam SEL_WIDTH = clog2((TOTAL_MASTER_CNT - 1)) ; 
    // ------------------------------------------------------------------------------
    // Register Declarations
    // ------------------------------------------------------------------------------
    reg [(ST_WIDTH - 1):0] cs_sm ; 
    reg [(ST_WIDTH - 1):0] ns_sm ; 
    reg arb_en ; 
    reg arb_en_Q ; 
    //reg                                           adv_cnt;
    reg ack ; 
    //reg [TOTAL_MASTER_CNT-1:0]                    req_wait;
    //reg [TOTAL_MASTER_CNT-1:0]                    req_in_Q;
    reg [(TOTAL_MASTER_CNT - 1):0] grant_Q ; 
    reg update_en ; 
    //reg [1:0]                                     arb_htrans;
    reg arb_hready ; 
    //wire                                          arb_hready_tmp;
    reg arb_hresp ; 
    //reg                                           ahbl_hreadyout;
    reg [1:0] ahbl_htrans ; 
    //reg                                           arb_swap;
    //reg                                           arb_start;
    reg [(SEL_WIDTH - 1):0] msel ; 
    reg [(SEL_WIDTH - 1):0] ssel ; 
    reg [(SEL_WIDTH - 1):0] ssel_data ; 
    // ------------------------------------------------------------------------------
    // Wire Declarations
    // ------------------------------------------------------------------------------
    wire [(TOTAL_MASTER_CNT - 1):0] req_in ; 
    //wire [TOTAL_MASTER_CNT-1:0]                   req_mask;
    wire [(TOTAL_MASTER_CNT - 1):0] grant ; 
    wire [(TOTAL_MASTER_CNT - 1):0] grant_nxt ; 
    //wire [TOTAL_MASTER_CNT-1:0]                   grant_masked;
    wire max_reached_w ; 
    wire cnt_en_w ; 
    wire arb_ack_w ; 
    wire [((TOTAL_MASTER_CNT * M_ADDR_WIDTH) - 1):0] reg_haddr_slv ; 
    wire [((TOTAL_MASTER_CNT * 3) - 1):0] reg_hburst_slv ; 
    wire [((TOTAL_MASTER_CNT * 3) - 1):0] reg_hsize_slv ; 
    wire [(TOTAL_MASTER_CNT - 1):0] reg_hmastlock_slv ; 
    wire [((TOTAL_MASTER_CNT * 4) - 1):0] reg_hprot_slv ; 
    wire [(TOTAL_MASTER_CNT - 1):0] reg_hwrite_slv ; 
    wire [(TOTAL_MASTER_CNT - 1):0] ahbl_hreadyout_w ; 
    wire start_of_burst_w ; 
    assign ahbl_hreadyout_w = ({TOTAL_MASTER_CNT{ahbl_hreadyout_mstr_i}} & grant) ; 
    // ------------------------------------------------------------------------------
    // Generate Blocks
    // ------------------------------------------------------------------------------
    genvar i ; 
    generate
        for (i = 0;(i < TOTAL_MASTER_CNT);i = (i + 1))
        begin : genblk1
            assign req_in[i] = ((ahbl_htrans_slv_i[(2 * i) +: 2] == NSEQ) && ahbl_hsel_slv_i[i]) ; 
        end
        assign ahbl_arb_en_slv_o = ({TOTAL_MASTER_CNT{arb_en}} & req_in) ; 
        assign ahbl_addr_stall_o = ((~ahbl_hreadyout_w) & req_in) ; 
        assign ahbl_start_slv_o = 1'b0 ; // {TOTAL_MASTER_CNT{arb_start}} & grant; // not used anymore
        assign ahbl_grant_slv_o = grant ; 
        assign ahbl_wait_slv_o = 1'b0 ; //req_wait; // not used anymore
    endgenerate
    // ------------------------------------------------------------------------------
    // Multiplexor
    // ------------------------------------------------------------------------------
    integer j ; 
    // ----------
    // To Master
    // ----------
    generate
        if ((OUTREG_EN == 0)) 
            begin : outreg_slv_off
                always
                    @(*)
                    begin
                        for (j = 0 ; (j < TOTAL_MASTER_CNT) ; j = (j + 1))
                            begin
                                if ((grant[j] || grant_Q[j])) 
                                    begin
                                        ahbl_hreadyout_slv_o[j] = arb_hready ;// ahbl_hreadyout_mstr_i;
                                    end
                                else
                                    begin
                                        // not granted
                                        ahbl_hreadyout_slv_o[j] = 1'b0 ;
                                    end
                                if (grant_Q[j]) 
                                    begin
                                        ahbl_hrdata_slv_o[(DATA_WIDTH * j) +: DATA_WIDTH] = ahbl_hrdata_mstr_i ;
                                        ahbl_hresp_slv_o[j] = arb_hresp ;// ahbl_hresp_mstr_i;
                                    end
                                else
                                    begin
                                        ahbl_hrdata_slv_o[(DATA_WIDTH * j) +: DATA_WIDTH] = {DATA_WIDTH{1'b0}} ;
                                        ahbl_hresp_slv_o[j] = 1'b0 ;
                                    end
                            end
                    end
            end
        else
            begin : outreg_slv_on
            end
    endgenerate
    // ---------
    // To Slave
    // ---------
    always// always @ *
        @(*)
        begin
            msel = 0 ;
            for (j = 0 ; (j < TOTAL_MASTER_CNT) ; j = (j + 1))
                begin
                    if ((grant == (1 << j))) 
                        begin
                            msel = j ;
                        end
                end
        end
    always
        @(posedge ahbl_hclk_i or 
            negedge ahbl_hresetn_i)
        begin
            if ((~ahbl_hresetn_i)) 
                begin
                    ssel_data <=  0 ;
                end
            else
                begin
                    if ((ahbl_hreadyout_mstr_i == 1)) 
                        begin
                            ssel_data <=  msel ;
                        end
                end
        end
    generate
        if ((OUTREG_EN == 0)) 
            begin : is_on_outreg_mstr_off
                always// always
                    @(*)
                    begin
                        ahbl_haddr_mstr_o = ahbl_haddr_slv_i[(M_ADDR_WIDTH * msel) +: M_ADDR_WIDTH] ;
                        ahbl_hburst_mstr_o = ahbl_hburst_slv_i[(3 * msel) +: 3] ;
                        ahbl_hsize_mstr_o = ahbl_hsize_slv_i[(3 * msel) +: 3] ;
                        ahbl_hwrite_mstr_o = ahbl_hwrite_slv_i[msel] ;
                        ahbl_hmastlock_mstr_o = ahbl_hmastlock_slv_i[msel] ;
                        ahbl_hprot_mstr_o = ahbl_hprot_slv_i[(4 * msel) +: 4] ;
                        ahbl_hready_mstr_o = (|(ahbl_hready_slv_i & grant)) ;// & ahbl_hreadyout_mstr_i;
                        ahbl_htrans_mstr_o = ahbl_htrans_slv_i[(2 * msel) +: 2] ;
                        ahbl_hsel_mstr_o = (|(ahbl_hsel_slv_i & grant)) ;
                        ahbl_htrans = ahbl_htrans_slv_i[(2 * msel) +: 2] ;// for internal 
                        ahbl_hwdata_mstr_o = ahbl_hwdata_slv_i[(DATA_WIDTH * ssel_data) +: DATA_WIDTH] ;
                    end
            end
        else
            begin : is_on_outreg_mstr_on
            end
    endgenerate
    //assign arb_hready_tmp = (|(grant & ahbl_hwrite_slv_i)) ? ahbl_hreadyout_mstr_i: 1'b0;
    assign start_of_burst_w = ((ahbl_htrans_mstr_o == NSEQ) & (ahbl_hburst_mstr_o != 3'b000)) ; 
    //assign ongoing_burst_w  = (ahbl_htrans_mstr_o == SEQ);
    // ------------------------------------------------------------------------------
    // Combinatorial Blocks
    // ------------------------------------------------------------------------------
    always
        @(*)
        begin
            ns_sm = cs_sm ;
            arb_en = 1'b0 ;
            ack = 1'b0 ;
            arb_hresp = ahbl_hresp_mstr_i ;
            arb_hready = ahbl_hreadyout_mstr_i ;
            //  arb_start   = 1'b0;
            case (1)
            (cs_sm == ST_IDLE) : 
                begin
                    if ((|req_in)) 
                        begin
                            if ((req_in != grant)) 
                                arb_en = (~start_of_burst_w) ;
                            else
                                // Only the already granted master maskes request
                                arb_en = 1'b0 ;
                            ns_sm = ST_REQ ;
                        end
                    else
                        // When IDLE and no request,
                        begin
                        end
                end
            (cs_sm == ST_REQ) : 
                begin
                    //if (|req_in && (req_in != grant) && ~start_of_burst_w) 
                    if ((((|req_in) && (req_in != grant)) && (ahbl_hburst_mstr_o == 3'b000))) 
                        arb_en = 1'b1 ;
                    else
                        arb_en = 1'b0 ;
                    if ((|grant)) 
                        begin
                            //        arb_start   = 1'b1;
                            ns_sm = (ahbl_hreadyout_mstr_i ? ST_ACTIVE : ST_REQ) ;
                        end
                end
            (cs_sm == ST_ACTIVE) : 
                begin
                    if ((((((ahbl_htrans == IDLE) || (ahbl_htrans == NSEQ)) && ahbl_hreadyout_mstr_i) && (~ahbl_hresp_mstr_i)) && (~start_of_burst_w))) 
                        begin
                            if ((|req_in)) 
                                begin
                                    if ((req_in != grant)) 
                                        arb_en = 1'b1 ;
                                    else
                                        arb_en = 1'b0 ;
                                    ns_sm = ST_REQ ;
                                end
                            else
                                begin
                                    ns_sm = ST_IDLE ;
                                end
                        end
                    else
                        if ((max_reached_w && (ahbl_htrans == NSEQ))) 
                            begin
                                ack = 1'b1 ;
                                ns_sm = ST_ERR0 ;
                            end
                end
            (cs_sm == ST_ERR0) : 
                begin
                    arb_hresp = 1'b1 ;
                    arb_hready = 1'b0 ;
                    ns_sm = ST_ERR1 ;
                end
            (cs_sm == ST_ERR1) : 
                begin
                    arb_hresp = 1'b1 ;
                    arb_hready = 1'b1 ;
                    ns_sm = ST_IDLE ;
                end
            default : 
                begin
                    ns_sm = ST_IDLE ;
                end
            endcase // case (1)
        end
    // ------------------------------------------------------------------------------
    // Sequential Blocks
    // ------------------------------------------------------------------------------
    always
        @(posedge ahbl_hclk_i or 
            negedge ahbl_hresetn_i)
        begin
            if ((~ahbl_hresetn_i)) 
                begin
                    cs_sm <=  ST_IDLE ;
                end
            else
                begin
                    cs_sm <=  ns_sm ;
                end
        end
    always
        @(posedge ahbl_hclk_i or 
            negedge ahbl_hresetn_i)
        begin
            if ((~ahbl_hresetn_i)) 
                begin
                    grant_Q <=  0 ;
                end
            else
                begin
                    grant_Q <=  (ahbl_hreadyout_mstr_i ? grant : grant_Q) ;
                end
        end
    // ------------------------------------------------------------------------------
    // Submodule Instantiations
    // ------------------------------------------------------------------------------
    generate
        if ((MAX_BURST_SIZE == 0)) 
            begin : dis_max_burst
                assign cnt_en_w = 1'b0 ; 
                assign arb_ack_w = 1'b0 ; 
            end
        else
            begin : en_max_burst
                assign cnt_en_w = (((cs_sm == ST_ACTIVE) & ahbl_hreadyout_mstr_i) & ((ahbl_htrans == SEQ) | (ahbl_htrans == NSEQ))) ; 
                assign arb_ack_w = ack ; 
            end
    endgenerate
    wire arb_en_w ; 
    assign arb_en_w = ((arb_en & ahbl_hready_mstr_o) & ahbl_hreadyout_mstr_i) ; 
    ahbl0_ipgen_lscc_ahbl_arbiter #(.TOTAL_MASTER_CNT(TOTAL_MASTER_CNT),
            .M_PRIO_IDX(M_PRIO_IDX),
            .DATA_WIDTH(DATA_WIDTH),
            .ARBITER_SCHEME(ARBITER_SCHEME),
            .MAX_BURST_SIZE(MAX_BURST_SIZE)) u_lscc_ahbl_arbiter (//AUTOINSTPARAM*/
            // Parameters
            /*/UTOINST*/ // Outputs
            .ahbl_gnt_o(grant), 
                .ahbl_gnt_nxt_o(grant_nxt), 
                .ahbl_max_reached_o(max_reached_w), 
                // Inputs
            .ahbl_hclk_i(ahbl_hclk_i), 
                .ahbl_hresetn_i(ahbl_hresetn_i), 
                .ahbl_arb_en_i(arb_en_w), 
                .ahbl_ack_i(arb_ack_w), 
                .ahbl_req_i(req_in), 
                .ahbl_adv_cnt_i(cnt_en_w)) ; 
    // ------------------------------------------------------------------------------
    // Function Definition
    // ------------------------------------------------------------------------------
    function integer clog2( 
        input integer depth )  ; 
        begin
            if ((depth == 0)) 
                clog2 = 1 ;
            else
                for (clog2 = 0 ; (depth > 0) ; clog2 = (clog2 + 1))
                    depth = (depth >> 1) ;
        end
    endfunction
endmodule



`timescale 1ns/1ps
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_bus.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
module ahbl0_ipgen_lscc_ahbl_bus #(parameter F = 8, 
        parameter M_ADDR_WIDTH = 32, 
        parameter FULL_DECODE_EN = 1, 
        parameter DATA_WIDTH = 32, 
        parameter TOTAL_SLAVE_CNT = 32, 
        parameter OUTREG_EN = 0, 
        parameter S0_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S0_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S0_ADDR_RANGE = {32'h400}, 
        parameter S1_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S1_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S1_ADDR_RANGE = {32'h400}, 
        parameter S2_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S2_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S2_ADDR_RANGE = {32'h400}, 
        parameter S3_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S3_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S3_ADDR_RANGE = {32'h400}, 
        parameter S4_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S4_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S4_ADDR_RANGE = {32'h400}, 
        parameter S5_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S5_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S5_ADDR_RANGE = {32'h400}, 
        parameter S6_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S6_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S6_ADDR_RANGE = {32'h400}, 
        parameter S7_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S7_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S7_ADDR_RANGE = {32'h400}, 
        parameter S8_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S8_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S8_ADDR_RANGE = {32'h400}, 
        parameter S9_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S9_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S9_ADDR_RANGE = {32'h400}, 
        parameter S10_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S10_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S10_ADDR_RANGE = {32'h400}, 
        parameter S11_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S11_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S11_ADDR_RANGE = {32'h400}, 
        parameter S12_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S12_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S12_ADDR_RANGE = {32'h400}, 
        parameter S13_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S13_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S13_ADDR_RANGE = {32'h400}, 
        parameter S14_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S14_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S14_ADDR_RANGE = {32'h400}, 
        parameter S15_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S15_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S15_ADDR_RANGE = {32'h400}, 
        parameter S16_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S16_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S16_ADDR_RANGE = {32'h400}, 
        parameter S17_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S17_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S17_ADDR_RANGE = {32'h400}, 
        parameter S18_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S18_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S18_ADDR_RANGE = {32'h400}, 
        parameter S19_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S19_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S19_ADDR_RANGE = {32'h400}, 
        parameter S20_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S20_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S20_ADDR_RANGE = {32'h400}, 
        parameter S21_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S21_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S21_ADDR_RANGE = {32'h400}, 
        parameter S22_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S22_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S22_ADDR_RANGE = {32'h400}, 
        parameter S23_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S23_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S23_ADDR_RANGE = {32'h400}, 
        parameter S24_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S24_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S24_ADDR_RANGE = {32'h400}, 
        parameter S25_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S25_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S25_ADDR_RANGE = {32'h400}, 
        parameter S26_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S26_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S26_ADDR_RANGE = {32'h400}, 
        parameter S27_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S27_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S27_ADDR_RANGE = {32'h400}, 
        parameter S28_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S28_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S28_ADDR_RANGE = {32'h400}, 
        parameter S29_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S29_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S29_ADDR_RANGE = {32'h400}, 
        parameter S30_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S30_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S30_ADDR_RANGE = {32'h400}, 
        parameter S31_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S31_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S31_ADDR_RANGE = {32'h400}) (
    // -----------------------------------------------------------------------------
    // Module Parameters
    // -----------------------------------------------------------------------------
    //parameter                                      K               = 32,
    // ------------------------------------------------------------------------------
    // Input/Output Ports
    // ------------------------------------------------------------------------------
    input ahbl_hclk_i, 
    input ahbl_hresetn_i, 
    // ----------------------------------------
    // AHB-Lite Master Interface (to/from master)
    // ----------------------------------------
    input ahbl_hsel_slv_i, 
    input [(M_ADDR_WIDTH - 1):0] ahbl_haddr_slv_i, 
    input [2:0] ahbl_hburst_slv_i, 
    input [2:0] ahbl_hsize_slv_i, 
    input ahbl_hmastlock_slv_i, 
    input [3:0] ahbl_hprot_slv_i, 
    input [1:0] ahbl_htrans_slv_i, 
    input [(DATA_WIDTH - 1):0] ahbl_hwdata_slv_i, 
    input ahbl_hwrite_slv_i, 
    input ahbl_hready_slv_i, 
    output wire ahbl_hreadyout_slv_o, 
    output wire ahbl_hresp_slv_o, 
    output wire [(DATA_WIDTH - 1):0] ahbl_hrdata_slv_o, 
    // -----------------------------------------
    // AHB-Lite Slave Interface (to/from slave)
    // -----------------------------------------
    output wire [(TOTAL_SLAVE_CNT - 1):0] ahbl_hsel_mstr_o, 
    output wire [((TOTAL_SLAVE_CNT * M_ADDR_WIDTH) - 1):0] ahbl_haddr_mstr_o, 
    output wire [((TOTAL_SLAVE_CNT * 3) - 1):0] ahbl_hburst_mstr_o, 
    output wire [((TOTAL_SLAVE_CNT * 3) - 1):0] ahbl_hsize_mstr_o, 
    output wire [(TOTAL_SLAVE_CNT - 1):0] ahbl_hmastlock_mstr_o, 
    output wire [((TOTAL_SLAVE_CNT * 4) - 1):0] ahbl_hprot_mstr_o, 
    output wire [((TOTAL_SLAVE_CNT * 2) - 1):0] ahbl_htrans_mstr_o, 
    output wire [((TOTAL_SLAVE_CNT * DATA_WIDTH) - 1):0] ahbl_hwdata_mstr_o, 
    output wire [(TOTAL_SLAVE_CNT - 1):0] ahbl_hwrite_mstr_o, 
    output wire [(TOTAL_SLAVE_CNT - 1):0] ahbl_hready_mstr_o, 
    input [(TOTAL_SLAVE_CNT - 1):0] ahbl_hreadyout_mstr_i, 
    input [(TOTAL_SLAVE_CNT - 1):0] ahbl_hresp_mstr_i, 
    input [((TOTAL_SLAVE_CNT * DATA_WIDTH) - 1):0] ahbl_hrdata_mstr_i) ;
    // ------------------------------------------------------------------------------
    // Local Parameters
    // ------------------------------------------------------------------------------
    localparam IDLE = 2'b00 ; 
    // ------------------------------------------------------------------------------
    // Wire Declarations
    // ------------------------------------------------------------------------------
    wire [(TOTAL_SLAVE_CNT - 1):0] ahbl_hsel_dec_w ; 
    wire [(DATA_WIDTH - 1):0] ahbl_hrdata_def_mstr_w ; 
    wire ahbl_hsel_def_mstr_w ; 
    wire ahbl_hsel_def_w ; 
    assign ahbl_hsel_def_mstr_w = ((ahbl_htrans_slv_i == 2'b00) ? 0 : ahbl_hsel_def_w) ; 
    // ------------------------------------------------------------------------------
    // Submodule Instantiations
    // ------------------------------------------------------------------------------
    // -----------------
    // AHB-Lite Decoder
    // -----------------
    ahbl0_ipgen_lscc_ahbl_decoder #(.F(F),
            .M_ADDR_WIDTH(M_ADDR_WIDTH),
            .FULL_DECODE_EN(FULL_DECODE_EN),
            .TOTAL_SLAVE_CNT(TOTAL_SLAVE_CNT),
            .S0_FRAGMENT_EN(S0_FRAGMENT_EN),
            .S0_BASE_ADDR(S0_BASE_ADDR),
            .S0_ADDR_RANGE(S0_ADDR_RANGE),
            .S1_FRAGMENT_EN(S1_FRAGMENT_EN),
            .S1_BASE_ADDR(S1_BASE_ADDR),
            .S1_ADDR_RANGE(S1_ADDR_RANGE),
            .S2_FRAGMENT_EN(S2_FRAGMENT_EN),
            .S2_BASE_ADDR(S2_BASE_ADDR),
            .S2_ADDR_RANGE(S2_ADDR_RANGE),
            .S3_FRAGMENT_EN(S3_FRAGMENT_EN),
            .S3_BASE_ADDR(S3_BASE_ADDR),
            .S3_ADDR_RANGE(S3_ADDR_RANGE),
            .S4_FRAGMENT_EN(S4_FRAGMENT_EN),
            .S4_BASE_ADDR(S4_BASE_ADDR),
            .S4_ADDR_RANGE(S4_ADDR_RANGE),
            .S5_FRAGMENT_EN(S5_FRAGMENT_EN),
            .S5_BASE_ADDR(S5_BASE_ADDR),
            .S5_ADDR_RANGE(S5_ADDR_RANGE),
            .S6_FRAGMENT_EN(S6_FRAGMENT_EN),
            .S6_BASE_ADDR(S6_BASE_ADDR),
            .S6_ADDR_RANGE(S6_ADDR_RANGE),
            .S7_FRAGMENT_EN(S7_FRAGMENT_EN),
            .S7_BASE_ADDR(S7_BASE_ADDR),
            .S7_ADDR_RANGE(S7_ADDR_RANGE),
            .S8_FRAGMENT_EN(S8_FRAGMENT_EN),
            .S8_BASE_ADDR(S8_BASE_ADDR),
            .S8_ADDR_RANGE(S8_ADDR_RANGE),
            .S9_FRAGMENT_EN(S9_FRAGMENT_EN),
            .S9_BASE_ADDR(S9_BASE_ADDR),
            .S9_ADDR_RANGE(S9_ADDR_RANGE),
            .S10_FRAGMENT_EN(S10_FRAGMENT_EN),
            .S10_BASE_ADDR(S10_BASE_ADDR),
            .S10_ADDR_RANGE(S10_ADDR_RANGE),
            .S11_FRAGMENT_EN(S11_FRAGMENT_EN),
            .S11_BASE_ADDR(S11_BASE_ADDR),
            .S11_ADDR_RANGE(S11_ADDR_RANGE),
            .S12_FRAGMENT_EN(S12_FRAGMENT_EN),
            .S12_BASE_ADDR(S12_BASE_ADDR),
            .S12_ADDR_RANGE(S12_ADDR_RANGE),
            .S13_FRAGMENT_EN(S13_FRAGMENT_EN),
            .S13_BASE_ADDR(S13_BASE_ADDR),
            .S13_ADDR_RANGE(S13_ADDR_RANGE),
            .S14_FRAGMENT_EN(S14_FRAGMENT_EN),
            .S14_BASE_ADDR(S14_BASE_ADDR),
            .S14_ADDR_RANGE(S14_ADDR_RANGE),
            .S15_FRAGMENT_EN(S15_FRAGMENT_EN),
            .S15_BASE_ADDR(S15_BASE_ADDR),
            .S15_ADDR_RANGE(S15_ADDR_RANGE),
            .S16_FRAGMENT_EN(S16_FRAGMENT_EN),
            .S16_BASE_ADDR(S16_BASE_ADDR),
            .S16_ADDR_RANGE(S16_ADDR_RANGE),
            .S17_FRAGMENT_EN(S17_FRAGMENT_EN),
            .S17_BASE_ADDR(S17_BASE_ADDR),
            .S17_ADDR_RANGE(S17_ADDR_RANGE),
            .S18_FRAGMENT_EN(S18_FRAGMENT_EN),
            .S18_BASE_ADDR(S18_BASE_ADDR),
            .S18_ADDR_RANGE(S18_ADDR_RANGE),
            .S19_FRAGMENT_EN(S19_FRAGMENT_EN),
            .S19_BASE_ADDR(S19_BASE_ADDR),
            .S19_ADDR_RANGE(S19_ADDR_RANGE),
            .S20_FRAGMENT_EN(S20_FRAGMENT_EN),
            .S20_BASE_ADDR(S20_BASE_ADDR),
            .S20_ADDR_RANGE(S20_ADDR_RANGE),
            .S21_FRAGMENT_EN(S21_FRAGMENT_EN),
            .S21_BASE_ADDR(S21_BASE_ADDR),
            .S21_ADDR_RANGE(S21_ADDR_RANGE),
            .S22_FRAGMENT_EN(S22_FRAGMENT_EN),
            .S22_BASE_ADDR(S22_BASE_ADDR),
            .S22_ADDR_RANGE(S22_ADDR_RANGE),
            .S23_FRAGMENT_EN(S23_FRAGMENT_EN),
            .S23_BASE_ADDR(S23_BASE_ADDR),
            .S23_ADDR_RANGE(S23_ADDR_RANGE),
            .S24_FRAGMENT_EN(S24_FRAGMENT_EN),
            .S24_BASE_ADDR(S24_BASE_ADDR),
            .S24_ADDR_RANGE(S24_ADDR_RANGE),
            .S25_FRAGMENT_EN(S25_FRAGMENT_EN),
            .S25_BASE_ADDR(S25_BASE_ADDR),
            .S25_ADDR_RANGE(S25_ADDR_RANGE),
            .S26_FRAGMENT_EN(S26_FRAGMENT_EN),
            .S26_BASE_ADDR(S26_BASE_ADDR),
            .S26_ADDR_RANGE(S26_ADDR_RANGE),
            .S27_FRAGMENT_EN(S27_FRAGMENT_EN),
            .S27_BASE_ADDR(S27_BASE_ADDR),
            .S27_ADDR_RANGE(S27_ADDR_RANGE),
            .S28_FRAGMENT_EN(S28_FRAGMENT_EN),
            .S28_BASE_ADDR(S28_BASE_ADDR),
            .S28_ADDR_RANGE(S28_ADDR_RANGE),
            .S29_FRAGMENT_EN(S29_FRAGMENT_EN),
            .S29_BASE_ADDR(S29_BASE_ADDR),
            .S29_ADDR_RANGE(S29_ADDR_RANGE),
            .S30_FRAGMENT_EN(S30_FRAGMENT_EN),
            .S30_BASE_ADDR(S30_BASE_ADDR),
            .S30_ADDR_RANGE(S30_ADDR_RANGE),
            .S31_FRAGMENT_EN(S31_FRAGMENT_EN),
            .S31_BASE_ADDR(S31_BASE_ADDR),
            .S31_ADDR_RANGE(S31_ADDR_RANGE)) u_lscc_ahbl_decoder (//AUTOINSTPARAM*/
            // Parameters
            //   .K                                   (K),
            //AUTOINST*/
            // Outputs
            .ahbl_hsel_o(ahbl_hsel_dec_w[(TOTAL_SLAVE_CNT - 1):0]), 
                .ahbl_hsel_def_o(ahbl_hsel_def_w), 
                // Inputs
            .enable_i(ahbl_hsel_slv_i), 
                .ahbl_haddr_i(ahbl_haddr_slv_i[(M_ADDR_WIDTH - 1):10])) ; 
    // ---------------------
    // AHB-Lite Multiplexor
    // ---------------------
    ahbl0_ipgen_lscc_ahbl_multiplexor #(.M_ADDR_WIDTH(M_ADDR_WIDTH),
            .DATA_WIDTH(DATA_WIDTH),
            .TOTAL_SLAVE_CNT(TOTAL_SLAVE_CNT),
            .OUTREG_EN(OUTREG_EN)) u_lscc_ahbl_multiplexor (//AUTOINSTPARAM*/
            // Parameters
            //   .K                                   (K),
            //AUTOINST*/
            // Outputs
            .ahbl_hreadyout_slv_o(ahbl_hreadyout_slv_o), 
                .ahbl_hresp_slv_o(ahbl_hresp_slv_o), 
                .ahbl_hrdata_slv_o(ahbl_hrdata_slv_o), 
                .ahbl_hsel_mstr_o(ahbl_hsel_mstr_o), 
                .ahbl_haddr_mstr_o(ahbl_haddr_mstr_o), 
                .ahbl_hburst_mstr_o(ahbl_hburst_mstr_o), 
                .ahbl_hsize_mstr_o(ahbl_hsize_mstr_o), 
                .ahbl_hmastlock_mstr_o(ahbl_hmastlock_mstr_o), 
                .ahbl_hprot_mstr_o(ahbl_hprot_mstr_o), 
                .ahbl_htrans_mstr_o(ahbl_htrans_mstr_o), 
                .ahbl_hwdata_mstr_o(ahbl_hwdata_mstr_o), 
                .ahbl_hwrite_mstr_o(ahbl_hwrite_mstr_o), 
                .ahbl_hready_mstr_o(ahbl_hready_mstr_o), 
                // Inputs
            .ahbl_hclk_i(ahbl_hclk_i), 
                .ahbl_hresetn_i(ahbl_hresetn_i), 
                .ahbl_hsel_slv_i(ahbl_hsel_slv_i), 
                .ahbl_hsel_dec_i(ahbl_hsel_dec_w[(TOTAL_SLAVE_CNT - 1):0]), 
                .ahbl_haddr_slv_i(ahbl_haddr_slv_i), 
                .ahbl_hburst_slv_i(ahbl_hburst_slv_i), 
                .ahbl_hsize_slv_i(ahbl_hsize_slv_i), 
                .ahbl_hmastlock_slv_i(ahbl_hmastlock_slv_i), 
                .ahbl_hprot_slv_i(ahbl_hprot_slv_i), 
                .ahbl_htrans_slv_i(ahbl_htrans_slv_i), 
                .ahbl_hwdata_slv_i(ahbl_hwdata_slv_i), 
                .ahbl_hwrite_slv_i(ahbl_hwrite_slv_i), 
                .ahbl_hready_slv_i(ahbl_hready_slv_i), 
                .ahbl_hreadyout_mstr_i(ahbl_hreadyout_mstr_i), 
                .ahbl_hresp_mstr_i(ahbl_hresp_mstr_i), 
                .ahbl_hrdata_mstr_i(ahbl_hrdata_mstr_i), 
                .ahbl_hsel_def_mstr_i(ahbl_hsel_def_mstr_w), 
                .ahbl_hready_def_mstr_i(ahbl_hready_def_mstr_w), 
                .ahbl_hresp_def_mstr_i(abhl_hresp_def_mstr_w), 
                .ahbl_hrdata_def_mstr_i(ahbl_hrdata_def_mstr_w[(DATA_WIDTH - 1):0])) ; 
    // -----------------------
    // AHB-Lite Default Slave
    // -----------------------
    ahbl0_ipgen_lscc_ahbl_default_slv #(.DATA_WIDTH(DATA_WIDTH)) u_lscc_ahbl_default_slv (//AUTOINSTPARAM*/
            // Parameters
            //AUTOINST*/
            // Outputs
            .ahbl_hready_def_o(ahbl_hready_def_mstr_w), 
                .ahbl_hresp_def_o(abhl_hresp_def_mstr_w), 
                .ahbl_hrdata_def_o(ahbl_hrdata_def_mstr_w[(DATA_WIDTH - 1):0]), 
                // Inputs
            .ahbl_hclk_i(ahbl_hclk_i), 
                .ahbl_hresetn_i(ahbl_hresetn_i), 
                .ahbl_hsel_i(ahbl_hsel_def_mstr_w), 
                .ahbl_htrans_i(ahbl_htrans_slv_i[1:0])) ; 
endmodule



`timescale 1ns/1ps
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

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     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_crossbar.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
module ahbl0_ipgen_lscc_ahbl_crossbar #(parameter F = 8, 
        parameter TOTAL_MASTER_CNT = 8, 
        parameter TOTAL_SLAVE_CNT = 8, 
        parameter M_ADDR_WIDTH = 32, 
        parameter FULL_DECODE_EN = 1, 
        parameter M_PRIO_WIDTH = clog2(TOTAL_MASTER_CNT), 
        parameter DATA_WIDTH = 32, 
        parameter OUTREG_EN = 0, 
        parameter S0_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S0_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S0_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S0_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S0_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S0_MAX_BURST_SIZE = 9'd0, 
        parameter S1_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S1_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S1_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S1_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S1_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S1_MAX_BURST_SIZE = 9'd0, 
        parameter S2_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S2_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S2_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S2_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S2_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S2_MAX_BURST_SIZE = 9'd0, 
        parameter S3_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S3_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S3_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S3_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S3_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S3_MAX_BURST_SIZE = 9'd0, 
        parameter S4_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S4_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S4_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S4_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S4_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S4_MAX_BURST_SIZE = 9'd0, 
        parameter S5_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S5_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S5_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S5_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S5_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S5_MAX_BURST_SIZE = 9'd0, 
        parameter S6_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S6_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S6_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S6_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S6_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S6_MAX_BURST_SIZE = 9'd0, 
        parameter S7_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S7_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S7_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S7_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S7_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S7_MAX_BURST_SIZE = 9'd0, 
        parameter S8_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S8_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S8_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S8_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S8_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S8_MAX_BURST_SIZE = 9'd0, 
        parameter S9_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S9_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S9_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S9_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S9_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S9_MAX_BURST_SIZE = 9'd0, 
        parameter S10_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S10_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S10_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S10_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S10_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S10_MAX_BURST_SIZE = 9'd0, 
        parameter S11_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S11_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S11_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S11_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S11_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S11_MAX_BURST_SIZE = 9'd0, 
        parameter S12_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S12_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S12_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S12_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S12_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S12_MAX_BURST_SIZE = 9'd0, 
        parameter S13_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S13_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S13_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S13_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S13_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S13_MAX_BURST_SIZE = 9'd0, 
        parameter S14_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S14_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S14_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S14_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S14_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S14_MAX_BURST_SIZE = 9'd0, 
        parameter S15_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S15_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S15_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S15_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S15_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S15_MAX_BURST_SIZE = 9'd0, 
        parameter S16_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S16_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S16_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S16_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S16_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S16_MAX_BURST_SIZE = 9'd0, 
        parameter S17_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S17_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S17_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S17_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S17_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S17_MAX_BURST_SIZE = 9'd0, 
        parameter S18_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S18_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S18_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S18_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S18_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S18_MAX_BURST_SIZE = 9'd0, 
        parameter S19_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S19_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S19_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S19_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S19_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S19_MAX_BURST_SIZE = 9'd0, 
        parameter S20_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S20_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S20_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S20_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S20_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S20_MAX_BURST_SIZE = 9'd0, 
        parameter S21_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S21_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S21_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S21_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S21_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S21_MAX_BURST_SIZE = 9'd0, 
        parameter S22_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S22_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S22_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S22_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S22_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S22_MAX_BURST_SIZE = 9'd0, 
        parameter S23_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S23_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S23_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S23_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S23_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S23_MAX_BURST_SIZE = 9'd0, 
        parameter S24_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S24_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S24_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S24_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S24_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S24_MAX_BURST_SIZE = 9'd0, 
        parameter S25_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S25_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S25_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S25_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S25_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S25_MAX_BURST_SIZE = 9'd0, 
        parameter S26_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S26_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S26_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S26_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S26_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S26_MAX_BURST_SIZE = 9'd0, 
        parameter S27_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S27_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S27_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S27_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S27_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S27_MAX_BURST_SIZE = 9'd0, 
        parameter S28_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S28_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S28_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S28_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S28_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S28_MAX_BURST_SIZE = 9'd0, 
        parameter S29_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S29_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S29_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S29_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S29_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S29_MAX_BURST_SIZE = 9'd0, 
        parameter S30_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S30_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S30_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S30_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S30_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S30_MAX_BURST_SIZE = 9'd0, 
        parameter S31_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S31_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S31_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S31_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S31_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S31_MAX_BURST_SIZE = 9'd0) (
    // -----------------------------------------------------------------------------
    // Module Parameters
    // -----------------------------------------------------------------------------
    // Maximum Fragment
    //--- Slave 0 -------------------------------------------------------------------
    //--- Slave 1 -------------------------------------------------------------------
    //--- Slave 2 -------------------------------------------------------------------
    //--- Slave 3 -------------------------------------------------------------------
    //--- Slave 4 -------------------------------------------------------------------
    //--- Slave 5 -------------------------------------------------------------------
    //--- Slave 6 -------------------------------------------------------------------
    //--- Slave 7 -------------------------------------------------------------------
    //--- Slave 8 -------------------------------------------------------------------
    //--- Slave 9 -------------------------------------------------------------------
    //--- Slave 10 ------------------------------------------------------------------
    //--- Slave 11 ------------------------------------------------------------------
    //--- Slave 12 ------------------------------------------------------------------
    //--- Slave 13 ------------------------------------------------------------------
    //--- Slave 14 ------------------------------------------------------------------
    //--- Slave 15 ------------------------------------------------------------------
    //--- Slave 16 ------------------------------------------------------------------
    //--- Slave 17 ------------------------------------------------------------------
    //--- Slave 18 ------------------------------------------------------------------
    //--- Slave 19 ------------------------------------------------------------------
    //--- Slave 20 ------------------------------------------------------------------
    //--- Slave 21 ------------------------------------------------------------------
    //--- Slave 22 ------------------------------------------------------------------
    //--- Slave 23 ------------------------------------------------------------------
    //--- Slave 24 ------------------------------------------------------------------
    //--- Slave 25 ------------------------------------------------------------------
    //--- Slave 26 ------------------------------------------------------------------
    //--- Slave 27 ------------------------------------------------------------------
    //--- Slave 28 ------------------------------------------------------------------
    //--- Slave 29 ------------------------------------------------------------------
    //--- Slave 30 ------------------------------------------------------------------
    //--- Slave 31 ------------------------------------------------------------------
    // ------------------------------------------------------------------------------
    // Input/Output Ports
    // ------------------------------------------------------------------------------
    input ahbl_hclk_i, 
    input ahbl_hresetn_i, 
    // -------------------------------------------
    // AHB-Lite Master Interface (to/from master)
    // -------------------------------------------
    input [(TOTAL_MASTER_CNT - 1):0] ahbl_hsel_slv_i, 
    input [((TOTAL_MASTER_CNT * M_ADDR_WIDTH) - 1):0] ahbl_haddr_slv_i, 
    input [((TOTAL_MASTER_CNT * 3) - 1):0] ahbl_hburst_slv_i, 
    input [((TOTAL_MASTER_CNT * 3) - 1):0] ahbl_hsize_slv_i, 
    input [(TOTAL_MASTER_CNT - 1):0] ahbl_hmastlock_slv_i, 
    input [((TOTAL_MASTER_CNT * 4) - 1):0] ahbl_hprot_slv_i, 
    input [((TOTAL_MASTER_CNT * 2) - 1):0] ahbl_htrans_slv_i, 
    input [((TOTAL_MASTER_CNT * DATA_WIDTH) - 1):0] ahbl_hwdata_slv_i, 
    input [(TOTAL_MASTER_CNT - 1):0] ahbl_hwrite_slv_i, 
    input [(TOTAL_MASTER_CNT - 1):0] ahbl_hready_slv_i, 
    output wire [(TOTAL_MASTER_CNT - 1):0] ahbl_hreadyout_slv_o, 
    //output wire [TOTAL_MASTER_CNT-1:0]            ahbl_hready_slv_o,
    output wire [(TOTAL_MASTER_CNT - 1):0] ahbl_hresp_slv_o, 
    output wire [((TOTAL_MASTER_CNT * DATA_WIDTH) - 1):0] ahbl_hrdata_slv_o, 
    // -----------------------------------------
    // AHB-Lite Slave Interface (to/from slave)
    // -----------------------------------------
    output wire [(TOTAL_SLAVE_CNT - 1):0] ahbl_hsel_mstr_o, 
    output wire [((TOTAL_SLAVE_CNT * M_ADDR_WIDTH) - 1):0] ahbl_haddr_mstr_o, 
    output wire [((TOTAL_SLAVE_CNT * 3) - 1):0] ahbl_hburst_mstr_o, 
    output wire [((TOTAL_SLAVE_CNT * 3) - 1):0] ahbl_hsize_mstr_o, 
    output wire [(TOTAL_SLAVE_CNT - 1):0] ahbl_hmastlock_mstr_o, 
    output wire [((TOTAL_SLAVE_CNT * 4) - 1):0] ahbl_hprot_mstr_o, 
    output wire [((TOTAL_SLAVE_CNT * 2) - 1):0] ahbl_htrans_mstr_o, 
    output wire [((TOTAL_SLAVE_CNT * DATA_WIDTH) - 1):0] ahbl_hwdata_mstr_o, 
    output wire [(TOTAL_SLAVE_CNT - 1):0] ahbl_hwrite_mstr_o, 
    output wire [(TOTAL_SLAVE_CNT - 1):0] ahbl_hready_mstr_o, 
    input [(TOTAL_SLAVE_CNT - 1):0] ahbl_hreadyout_mstr_i, 
    input [(TOTAL_SLAVE_CNT - 1):0] ahbl_hresp_mstr_i, 
    input [((TOTAL_SLAVE_CNT * DATA_WIDTH) - 1):0] ahbl_hrdata_mstr_i) ;
    // ------------------------------------------------------------------------------
    // Local Parameters
    // ------------------------------------------------------------------------------
    localparam M = TOTAL_MASTER_CNT ; 
    localparam N = TOTAL_SLAVE_CNT ; 
    localparam AW = M_ADDR_WIDTH ; 
    localparam DW = DATA_WIDTH ; 
    localparam [((N * 3) - 1):0] ARBITER_SCHEME = {S31_ARBITER_SCHEME,
                S30_ARBITER_SCHEME,
                S29_ARBITER_SCHEME,
                S28_ARBITER_SCHEME,
                S27_ARBITER_SCHEME,
                S26_ARBITER_SCHEME,
                S25_ARBITER_SCHEME,
                S24_ARBITER_SCHEME,
                S23_ARBITER_SCHEME,
                S22_ARBITER_SCHEME,
                S21_ARBITER_SCHEME,
                S20_ARBITER_SCHEME,
                S19_ARBITER_SCHEME,
                S18_ARBITER_SCHEME,
                S17_ARBITER_SCHEME,
                S16_ARBITER_SCHEME,
                S15_ARBITER_SCHEME,
                S14_ARBITER_SCHEME,
                S13_ARBITER_SCHEME,
                S12_ARBITER_SCHEME,
                S11_ARBITER_SCHEME,
                S10_ARBITER_SCHEME,
                S9_ARBITER_SCHEME,
                S8_ARBITER_SCHEME,
                S7_ARBITER_SCHEME,
                S6_ARBITER_SCHEME,
                S5_ARBITER_SCHEME,
                S4_ARBITER_SCHEME,
                S3_ARBITER_SCHEME,
                S2_ARBITER_SCHEME,
                S1_ARBITER_SCHEME,
                S0_ARBITER_SCHEME} ; 
    localparam [(((M * N) * M_PRIO_WIDTH) - 1):0] M_PRIO_IDX = {S31_M_PRIO_IDX,
                S30_M_PRIO_IDX,
                S29_M_PRIO_IDX,
                S28_M_PRIO_IDX,
                S27_M_PRIO_IDX,
                S26_M_PRIO_IDX,
                S25_M_PRIO_IDX,
                S24_M_PRIO_IDX,
                S23_M_PRIO_IDX,
                S22_M_PRIO_IDX,
                S21_M_PRIO_IDX,
                S20_M_PRIO_IDX,
                S19_M_PRIO_IDX,
                S18_M_PRIO_IDX,
                S17_M_PRIO_IDX,
                S16_M_PRIO_IDX,
                S15_M_PRIO_IDX,
                S14_M_PRIO_IDX,
                S13_M_PRIO_IDX,
                S12_M_PRIO_IDX,
                S11_M_PRIO_IDX,
                S10_M_PRIO_IDX,
                S9_M_PRIO_IDX,
                S8_M_PRIO_IDX,
                S7_M_PRIO_IDX,
                S6_M_PRIO_IDX,
                S5_M_PRIO_IDX,
                S4_M_PRIO_IDX,
                S3_M_PRIO_IDX,
                S2_M_PRIO_IDX,
                S1_M_PRIO_IDX,
                S0_M_PRIO_IDX} ; 
    localparam [((N * 9) - 1):0] MAX_BURST_SIZE = {S31_MAX_BURST_SIZE,
                S30_MAX_BURST_SIZE,
                S29_MAX_BURST_SIZE,
                S28_MAX_BURST_SIZE,
                S27_MAX_BURST_SIZE,
                S26_MAX_BURST_SIZE,
                S25_MAX_BURST_SIZE,
                S24_MAX_BURST_SIZE,
                S23_MAX_BURST_SIZE,
                S22_MAX_BURST_SIZE,
                S21_MAX_BURST_SIZE,
                S20_MAX_BURST_SIZE,
                S19_MAX_BURST_SIZE,
                S18_MAX_BURST_SIZE,
                S17_MAX_BURST_SIZE,
                S16_MAX_BURST_SIZE,
                S15_MAX_BURST_SIZE,
                S14_MAX_BURST_SIZE,
                S13_MAX_BURST_SIZE,
                S12_MAX_BURST_SIZE,
                S11_MAX_BURST_SIZE,
                S10_MAX_BURST_SIZE,
                S9_MAX_BURST_SIZE,
                S8_MAX_BURST_SIZE,
                S7_MAX_BURST_SIZE,
                S6_MAX_BURST_SIZE,
                S5_MAX_BURST_SIZE,
                S4_MAX_BURST_SIZE,
                S3_MAX_BURST_SIZE,
                S2_MAX_BURST_SIZE,
                S1_MAX_BURST_SIZE,
                S0_MAX_BURST_SIZE} ; 
    // ------------------------------------------------------------------------------
    // Wire Declarations
    // ------------------------------------------------------------------------------
    wire [((M * N) - 1):0] ahbl_bus_m2s_hsel ; 
    wire [(((M * N) * M_ADDR_WIDTH) - 1):0] ahbl_bus_m2s_haddr ; 
    wire [(((M * N) * 3) - 1):0] ahbl_bus_m2s_hburst ; 
    wire [(((M * N) * 3) - 1):0] ahbl_bus_m2s_hsize ; 
    wire [((M * N) - 1):0] ahbl_bus_m2s_hmastlock ; 
    wire [(((M * N) * 4) - 1):0] ahbl_bus_m2s_hprot ; 
    wire [(((M * N) * 2) - 1):0] ahbl_bus_m2s_htrans ; 
    wire [(((M * N) * DATA_WIDTH) - 1):0] ahbl_bus_m2s_hwdata ; 
    wire [((M * N) - 1):0] ahbl_bus_m2s_hwrite ; 
    wire [((M * N) - 1):0] ahbl_bus_m2s_hready ; 
    wire [((M * N) - 1):0] ahbl_bus_s2m_hreadyout ; 
    wire [((M * N) - 1):0] ahbl_bus_s2m_hresp ; 
    wire [(((M * N) * DATA_WIDTH) - 1):0] ahbl_bus_s2m_hrdata ; 
    wire [((M * N) - 1):0] ahbl_arb_m2s_hsel ; 
    wire [(((M * N) * M_ADDR_WIDTH) - 1):0] ahbl_arb_m2s_haddr ; 
    wire [(((M * N) * 3) - 1):0] ahbl_arb_m2s_hburst ; 
    wire [(((M * N) * 3) - 1):0] ahbl_arb_m2s_hsize ; 
    wire [((M * N) - 1):0] ahbl_arb_m2s_hmastlock ; 
    wire [(((M * N) * 4) - 1):0] ahbl_arb_m2s_hprot ; 
    wire [(((M * N) * 2) - 1):0] ahbl_arb_m2s_htrans ; 
    wire [(((M * N) * DATA_WIDTH) - 1):0] ahbl_arb_m2s_hwdata ; 
    wire [((M * N) - 1):0] ahbl_arb_m2s_hwrite ; 
    wire [((M * N) - 1):0] ahbl_arb_m2s_hready ; 
    wire [((M * N) - 1):0] ahbl_arb_s2m_hreadyout ; 
    wire [((M * N) - 1):0] ahbl_arb_s2m_hresp ; 
    wire [(((M * N) * DATA_WIDTH) - 1):0] ahbl_arb_s2m_hrdata ; 
    wire [(M - 1):0] ahbl_hreadyout_slv_w ; 
    wire [(M - 1):0] ahbl_hready_slv_w ; 
    wire [((M * 2) - 1):0] ahbl_htrans_slv_w ; 
    wire [((M * M_ADDR_WIDTH) - 1):0] ahbl_haddr_slv_w ; 
    wire [((M * 3) - 1):0] ahbl_hburst_slv_w ; 
    wire [((M * 3) - 1):0] ahbl_hsize_slv_w ; 
    wire [(M - 1):0] ahbl_hmastlock_slv_w ; 
    wire [((M * 4) - 1):0] ahbl_hprot_slv_w ; 
    wire [(M - 1):0] ahbl_hwrite_slv_w ; 
    wire [(M - 1):0] ahbl_hsel_slv_w ; 
    wire [((M * N) - 1):0] ahbl_arb_en_w ; 
    wire [((M * N) - 1):0] ahbl_arb_en_ored_s2m_w ; 
    wire [((M * N) - 1):0] ahbl_start_w ; 
    wire [((M * N) - 1):0] ahbl_start_ored_s2m_w ; 
    wire [((M * N) - 1):0] ahbl_wait_s2m_w ; 
    wire [((M * N) - 1):0] ahbl_wait_ored_s2m_w ; 
    wire [((M * N) - 1):0] ahbl_grant_s2m_w ; 
    wire [((M * N) - 1):0] ahbl_grant_ored_s2m_w ; 
    wire [((M * N) - 1):0] ahbl_addr_stall_w ; 
    wire [((M * N) - 1):0] ahbl_addr_stall_ored_s2m_w ; 
    // ------------------------------------------------------------------------------
    // Assign Statements
    // ------------------------------------------------------------------------------
    genvar i, 
        j ; 
    generate
        for (i = 0;(i < M);i = (i + 1))
        begin : intercon
            for (j = 0;(j < N);j = (j + 1))
            begin : genblk1
                assign ahbl_arb_m2s_hsel[((M * j) + i)] = ahbl_bus_m2s_hsel[((N * i) + j)] ; 
                assign ahbl_arb_m2s_haddr[(AW * ((M * j) + i)) +: AW] = ahbl_bus_m2s_haddr[(AW * ((N * i) + j)) +: AW] ; 
                assign ahbl_arb_m2s_hburst[(3 * ((M * j) + i)) +: 3] = ahbl_bus_m2s_hburst[(3 * ((N * i) + j)) +: 3] ; 
                assign ahbl_arb_m2s_hsize[(3 * ((M * j) + i)) +: 3] = ahbl_bus_m2s_hsize[(3 * ((N * i) + j)) +: 3] ; 
                assign ahbl_arb_m2s_hmastlock[((M * j) + i)] = ahbl_bus_m2s_hmastlock[((N * i) + j)] ; 
                assign ahbl_arb_m2s_hprot[(4 * ((M * j) + i)) +: 4] = ahbl_bus_m2s_hprot[(4 * ((N * i) + j)) +: 4] ; 
                assign ahbl_arb_m2s_htrans[(2 * ((M * j) + i)) +: 2] = ahbl_bus_m2s_htrans[(2 * ((N * i) + j)) +: 2] ; 
                assign ahbl_arb_m2s_hwdata[(DW * ((M * j) + i)) +: DW] = ahbl_bus_m2s_hwdata[(DW * ((N * i) + j)) +: DW] ; 
                assign ahbl_arb_m2s_hwrite[((M * j) + i)] = ahbl_bus_m2s_hwrite[((N * i) + j)] ; 
                assign ahbl_arb_m2s_hready[((M * j) + i)] = ahbl_bus_m2s_hready[((N * i) + j)] ; 
                assign ahbl_bus_s2m_hreadyout[((N * i) + j)] = ahbl_arb_s2m_hreadyout[((M * j) + i)] ; 
                assign ahbl_bus_s2m_hresp[((N * i) + j)] = ahbl_arb_s2m_hresp[((M * j) + i)] ; 
                assign ahbl_bus_s2m_hrdata[(DW * ((N * i) + j)) +: DW] = ahbl_arb_s2m_hrdata[(DW * ((M * j) + i)) +: DW] ; 
                assign ahbl_arb_en_ored_s2m_w[((N * i) + j)] = ahbl_arb_en_w[((M * j) + i)] ; 
                assign ahbl_start_ored_s2m_w[((N * i) + j)] = ahbl_start_w[((M * j) + i)] ; 
                assign ahbl_wait_ored_s2m_w[((N * i) + j)] = ahbl_wait_s2m_w[((M * j) + i)] ; 
                assign ahbl_grant_ored_s2m_w[((N * i) + j)] = ahbl_grant_s2m_w[((M * j) + i)] ; 
                assign ahbl_addr_stall_ored_s2m_w[((N * i) + j)] = ahbl_addr_stall_w[((M * j) + i)] ; 
            end
        end
    endgenerate
    // ------------------------------------------------------------------------------
    // Submodule Instantiation(s)
    // ------------------------------------------------------------------------------
    generate
        for (i = 0;(i < TOTAL_MASTER_CNT);i = (i + 1))
        begin : input_stage_reg
            // -------------
            // Input Stage
            // -------------    
            ahbl0_ipgen_lscc_ahbl_input_stage #(.M_ADDR_WIDTH(M_ADDR_WIDTH)) u_lscc_ahbl_input_stage (/*AUTOINSTPARAM*/ // Parameters
                    /*AUTOINST*/ // Outputs
                    .ahbl_hreadyout_slv_o(ahbl_hreadyout_slv_o[i]), 
                        .ahbl_hready_slv_i(ahbl_hready_slv_i[i]), 
                        .ahbl_htrans_slv_o(ahbl_htrans_slv_w[(2 * i) +: 2]), 
                        .ahbl_haddr_slv_o(ahbl_haddr_slv_w[(M_ADDR_WIDTH * i) +: M_ADDR_WIDTH]), 
                        .ahbl_hburst_slv_o(ahbl_hburst_slv_w[(3 * i) +: 3]), 
                        .ahbl_hsize_slv_o(ahbl_hsize_slv_w[(3 * i) +: 3]), 
                        .ahbl_hmastlock_slv_o(ahbl_hmastlock_slv_w[i]), 
                        .ahbl_hprot_slv_o(ahbl_hprot_slv_w[(4 * i) +: 4]), 
                        .ahbl_hwrite_slv_o(ahbl_hwrite_slv_w[i]), 
                        .ahbl_hsel_slv_o(ahbl_hsel_slv_w[i]), 
                        // Inputs
                    .ahbl_hclk_i(ahbl_hclk_i), 
                        .ahbl_hresetn_i(ahbl_hresetn_i), 
                        .ahbl_arb_en_i((|ahbl_arb_en_ored_s2m_w[(N * i) +: N])), 
                        .ahbl_start_i((|ahbl_start_ored_s2m_w[(N * i) +: N])), 
                        .ahbl_grant_i((|ahbl_grant_ored_s2m_w[(N * i) +: N])), 
                        .ahbl_wait_i((|ahbl_wait_ored_s2m_w[(N * i) +: N])), 
                        .ahbl_addr_stall_i((|ahbl_addr_stall_ored_s2m_w[(N * i) +: N])), 
                        .ahbl_hreadyout_slv_i(ahbl_hreadyout_slv_w[i]), 
                        .ahbl_hready_slv_o(ahbl_hready_slv_w[i]), 
                        .ahbl_htrans_slv_i(ahbl_htrans_slv_i[(2 * i) +: 2]), 
                        .ahbl_haddr_slv_i(ahbl_haddr_slv_i[(M_ADDR_WIDTH * i) +: M_ADDR_WIDTH]), 
                        .ahbl_hburst_slv_i(ahbl_hburst_slv_i[(3 * i) +: 3]), 
                        .ahbl_hsize_slv_i(ahbl_hsize_slv_i[(3 * i) +: 3]), 
                        .ahbl_hmastlock_slv_i(ahbl_hmastlock_slv_i[i]), 
                        .ahbl_hprot_slv_i(ahbl_hprot_slv_i[(4 * i) +: 4]), 
                        .ahbl_hwrite_slv_i(ahbl_hwrite_slv_i[i]), 
                        .ahbl_hsel_slv_i(ahbl_hsel_slv_i[i]), 
                        .ahbl_hresp_slv_i(ahbl_hresp_slv_o[i])) ; 
        end
    endgenerate
    generate
        for (i = 0;(i < M);i = (i + 1))
        begin : bus
            // -------------
            // AHB-Lite Bus
            // -------------
            ahbl0_ipgen_lscc_ahbl_bus #(.M_ADDR_WIDTH(M_ADDR_WIDTH),
                    .FULL_DECODE_EN(FULL_DECODE_EN),
                    .DATA_WIDTH(DATA_WIDTH),
                    .TOTAL_SLAVE_CNT(TOTAL_SLAVE_CNT),
                    .OUTREG_EN(OUTREG_EN),
                    .S0_FRAGMENT_EN(S0_FRAGMENT_EN),
                    .S0_BASE_ADDR(S0_BASE_ADDR),
                    .S0_ADDR_RANGE(S0_ADDR_RANGE),
                    .S1_FRAGMENT_EN(S1_FRAGMENT_EN),
                    .S1_BASE_ADDR(S1_BASE_ADDR),
                    .S1_ADDR_RANGE(S1_ADDR_RANGE),
                    .S2_FRAGMENT_EN(S2_FRAGMENT_EN),
                    .S2_BASE_ADDR(S2_BASE_ADDR),
                    .S2_ADDR_RANGE(S2_ADDR_RANGE),
                    .S3_FRAGMENT_EN(S3_FRAGMENT_EN),
                    .S3_BASE_ADDR(S3_BASE_ADDR),
                    .S3_ADDR_RANGE(S3_ADDR_RANGE),
                    .S4_FRAGMENT_EN(S4_FRAGMENT_EN),
                    .S4_BASE_ADDR(S4_BASE_ADDR),
                    .S4_ADDR_RANGE(S4_ADDR_RANGE),
                    .S5_FRAGMENT_EN(S5_FRAGMENT_EN),
                    .S5_BASE_ADDR(S5_BASE_ADDR),
                    .S5_ADDR_RANGE(S5_ADDR_RANGE),
                    .S6_FRAGMENT_EN(S6_FRAGMENT_EN),
                    .S6_BASE_ADDR(S6_BASE_ADDR),
                    .S6_ADDR_RANGE(S6_ADDR_RANGE),
                    .S7_FRAGMENT_EN(S7_FRAGMENT_EN),
                    .S7_BASE_ADDR(S7_BASE_ADDR),
                    .S7_ADDR_RANGE(S7_ADDR_RANGE),
                    .S8_FRAGMENT_EN(S8_FRAGMENT_EN),
                    .S8_BASE_ADDR(S8_BASE_ADDR),
                    .S8_ADDR_RANGE(S8_ADDR_RANGE),
                    .S9_FRAGMENT_EN(S9_FRAGMENT_EN),
                    .S9_BASE_ADDR(S9_BASE_ADDR),
                    .S9_ADDR_RANGE(S9_ADDR_RANGE),
                    .S10_FRAGMENT_EN(S10_FRAGMENT_EN),
                    .S10_BASE_ADDR(S10_BASE_ADDR),
                    .S10_ADDR_RANGE(S10_ADDR_RANGE),
                    .S11_FRAGMENT_EN(S11_FRAGMENT_EN),
                    .S11_BASE_ADDR(S11_BASE_ADDR),
                    .S11_ADDR_RANGE(S11_ADDR_RANGE),
                    .S12_FRAGMENT_EN(S12_FRAGMENT_EN),
                    .S12_BASE_ADDR(S12_BASE_ADDR),
                    .S12_ADDR_RANGE(S12_ADDR_RANGE),
                    .S13_FRAGMENT_EN(S13_FRAGMENT_EN),
                    .S13_BASE_ADDR(S13_BASE_ADDR),
                    .S13_ADDR_RANGE(S13_ADDR_RANGE),
                    .S14_FRAGMENT_EN(S14_FRAGMENT_EN),
                    .S14_BASE_ADDR(S14_BASE_ADDR),
                    .S14_ADDR_RANGE(S14_ADDR_RANGE),
                    .S15_FRAGMENT_EN(S15_FRAGMENT_EN),
                    .S15_BASE_ADDR(S15_BASE_ADDR),
                    .S15_ADDR_RANGE(S15_ADDR_RANGE),
                    .S16_FRAGMENT_EN(S16_FRAGMENT_EN),
                    .S16_BASE_ADDR(S16_BASE_ADDR),
                    .S16_ADDR_RANGE(S16_ADDR_RANGE),
                    .S17_FRAGMENT_EN(S17_FRAGMENT_EN),
                    .S17_BASE_ADDR(S17_BASE_ADDR),
                    .S17_ADDR_RANGE(S17_ADDR_RANGE),
                    .S18_FRAGMENT_EN(S18_FRAGMENT_EN),
                    .S18_BASE_ADDR(S18_BASE_ADDR),
                    .S18_ADDR_RANGE(S18_ADDR_RANGE),
                    .S19_FRAGMENT_EN(S19_FRAGMENT_EN),
                    .S19_BASE_ADDR(S19_BASE_ADDR),
                    .S19_ADDR_RANGE(S19_ADDR_RANGE),
                    .S20_FRAGMENT_EN(S20_FRAGMENT_EN),
                    .S20_BASE_ADDR(S20_BASE_ADDR),
                    .S20_ADDR_RANGE(S20_ADDR_RANGE),
                    .S21_FRAGMENT_EN(S21_FRAGMENT_EN),
                    .S21_BASE_ADDR(S21_BASE_ADDR),
                    .S21_ADDR_RANGE(S21_ADDR_RANGE),
                    .S22_FRAGMENT_EN(S22_FRAGMENT_EN),
                    .S22_BASE_ADDR(S22_BASE_ADDR),
                    .S22_ADDR_RANGE(S22_ADDR_RANGE),
                    .S23_FRAGMENT_EN(S23_FRAGMENT_EN),
                    .S23_BASE_ADDR(S23_BASE_ADDR),
                    .S23_ADDR_RANGE(S23_ADDR_RANGE),
                    .S24_FRAGMENT_EN(S24_FRAGMENT_EN),
                    .S24_BASE_ADDR(S24_BASE_ADDR),
                    .S24_ADDR_RANGE(S24_ADDR_RANGE),
                    .S25_FRAGMENT_EN(S25_FRAGMENT_EN),
                    .S25_BASE_ADDR(S25_BASE_ADDR),
                    .S25_ADDR_RANGE(S25_ADDR_RANGE),
                    .S26_FRAGMENT_EN(S26_FRAGMENT_EN),
                    .S26_BASE_ADDR(S26_BASE_ADDR),
                    .S26_ADDR_RANGE(S26_ADDR_RANGE),
                    .S27_FRAGMENT_EN(S27_FRAGMENT_EN),
                    .S27_BASE_ADDR(S27_BASE_ADDR),
                    .S27_ADDR_RANGE(S27_ADDR_RANGE),
                    .S28_FRAGMENT_EN(S28_FRAGMENT_EN),
                    .S28_BASE_ADDR(S28_BASE_ADDR),
                    .S28_ADDR_RANGE(S28_ADDR_RANGE),
                    .S29_FRAGMENT_EN(S29_FRAGMENT_EN),
                    .S29_BASE_ADDR(S29_BASE_ADDR),
                    .S29_ADDR_RANGE(S29_ADDR_RANGE),
                    .S30_FRAGMENT_EN(S30_FRAGMENT_EN),
                    .S30_BASE_ADDR(S30_BASE_ADDR),
                    .S30_ADDR_RANGE(S30_ADDR_RANGE),
                    .S31_FRAGMENT_EN(S31_FRAGMENT_EN),
                    .S31_BASE_ADDR(S31_BASE_ADDR),
                    .S31_ADDR_RANGE(S31_ADDR_RANGE)) u_lscc_ahbl_bus (/*AUTOINSTPARAM*/ // Parameters
                    //   .K                                   (K),
                    /*AUTOINST*/ // Outputs
                    .ahbl_hreadyout_slv_o(ahbl_hreadyout_slv_w[i]),  //(ahbl_hready_slv_o[i]),
                    .ahbl_hresp_slv_o(ahbl_hresp_slv_o[i]), 
                        .ahbl_hrdata_slv_o(ahbl_hrdata_slv_o[(DW * i) +: DW]), 
                        .ahbl_hsel_mstr_o(ahbl_bus_m2s_hsel[(N * i) +: N]), 
                        .ahbl_haddr_mstr_o(ahbl_bus_m2s_haddr[((N * AW) * i) +: (N * AW)]), 
                        .ahbl_hburst_mstr_o(ahbl_bus_m2s_hburst[((N * 3) * i) +: (N * 3)]), 
                        .ahbl_hsize_mstr_o(ahbl_bus_m2s_hsize[((N * 3) * i) +: (N * 3)]), 
                        .ahbl_hmastlock_mstr_o(ahbl_bus_m2s_hmastlock[(N * i) +: N]), 
                        .ahbl_hprot_mstr_o(ahbl_bus_m2s_hprot[((N * 4) * i) +: (N * 4)]), 
                        .ahbl_htrans_mstr_o(ahbl_bus_m2s_htrans[((N * 2) * i) +: (N * 2)]), 
                        .ahbl_hwdata_mstr_o(ahbl_bus_m2s_hwdata[((N * DW) * i) +: (N * DW)]), 
                        .ahbl_hwrite_mstr_o(ahbl_bus_m2s_hwrite[(N * i) +: N]), 
                        .ahbl_hready_mstr_o(ahbl_bus_m2s_hready[(N * i) +: N]), 
                        // Inputs
                    .ahbl_hclk_i(ahbl_hclk_i), 
                        .ahbl_hresetn_i(ahbl_hresetn_i), 
                        .ahbl_hsel_slv_i(ahbl_hsel_slv_w[i]),  //(ahbl_hsel_slv_i[i]),
                    .ahbl_haddr_slv_i(ahbl_haddr_slv_w[(AW * i) +: AW]), 
                        .ahbl_hburst_slv_i(ahbl_hburst_slv_w[(3 * i) +: 3]), 
                        .ahbl_hsize_slv_i(ahbl_hsize_slv_w[(3 * i) +: 3]), 
                        .ahbl_hmastlock_slv_i(ahbl_hmastlock_slv_w[i]), 
                        .ahbl_hprot_slv_i(ahbl_hprot_slv_w[(4 * i) +: 4]), 
                        .ahbl_htrans_slv_i(ahbl_htrans_slv_w[(2 * i) +: 2]), 
                        .ahbl_hwdata_slv_i(ahbl_hwdata_slv_i[(DW * i) +: DW]), 
                        .ahbl_hwrite_slv_i(ahbl_hwrite_slv_w[i]), 
                        .ahbl_hready_slv_i(ahbl_hready_slv_w[i]), 
                        .ahbl_hreadyout_mstr_i(ahbl_bus_s2m_hreadyout[(N * i) +: N]), 
                        .ahbl_hresp_mstr_i(ahbl_bus_s2m_hresp[(N * i) +: N]), 
                        .ahbl_hrdata_mstr_i(ahbl_bus_s2m_hrdata[((N * DW) * i) +: (N * DW)])) ; 
            // for (i = 0; i < M; i = i + 1)
        end
    endgenerate
    generate
        for (i = 0;(i < N);i = (i + 1))
        begin : arbiter_mux
            // -----------------------------
            // AHB-Lite Arbiter-Multiplexor
            // -----------------------------
            ahbl0_ipgen_lscc_ahbl_arbmux #(.TOTAL_MASTER_CNT(TOTAL_MASTER_CNT),
                    .M_ADDR_WIDTH(M_ADDR_WIDTH),
                    .M_PRIO_WIDTH(M_PRIO_WIDTH),
                    .M_PRIO_IDX(M_PRIO_IDX[((M * M_PRIO_WIDTH) * i) +: (M * M_PRIO_WIDTH)]),
                    .DATA_WIDTH(DATA_WIDTH),
                    .OUTREG_EN(OUTREG_EN),
                    .ARBITER_SCHEME(ARBITER_SCHEME[(3 * i) +: 3]),
                    .MAX_BURST_SIZE(MAX_BURST_SIZE[(9 * i) +: 9])) u_lscc_ahbl_arbmux (//AUTOINSTPARAM*/
                    // Parameters
                    //AUTOINST*/
                    // Outputs
                    .ahbl_hreadyout_slv_o(ahbl_arb_s2m_hreadyout[(M * i) +: M]), 
                        .ahbl_hresp_slv_o(ahbl_arb_s2m_hresp[(M * i) +: M]), 
                        .ahbl_hrdata_slv_o(ahbl_arb_s2m_hrdata[((M * DW) * i) +: (M * DW)]), 
                        .ahbl_hsel_mstr_o(ahbl_hsel_mstr_o[i]), 
                        .ahbl_haddr_mstr_o(ahbl_haddr_mstr_o[(AW * i) +: AW]), 
                        .ahbl_hburst_mstr_o(ahbl_hburst_mstr_o[(3 * i) +: 3]), 
                        .ahbl_hsize_mstr_o(ahbl_hsize_mstr_o[(3 * i) +: 3]), 
                        .ahbl_hmastlock_mstr_o(ahbl_hmastlock_mstr_o[i]), 
                        .ahbl_hprot_mstr_o(ahbl_hprot_mstr_o[(4 * i) +: 4]), 
                        .ahbl_htrans_mstr_o(ahbl_htrans_mstr_o[(2 * i) +: 2]), 
                        .ahbl_hwdata_mstr_o(ahbl_hwdata_mstr_o[(DW * i) +: DW]), 
                        .ahbl_hwrite_mstr_o(ahbl_hwrite_mstr_o[i]), 
                        .ahbl_hready_mstr_o(ahbl_hready_mstr_o[i]), 
                        .ahbl_arb_en_slv_o(ahbl_arb_en_w[(M * i) +: M]), 
                        .ahbl_start_slv_o(ahbl_start_w[(M * i) +: M]), 
                        .ahbl_grant_slv_o(ahbl_grant_s2m_w[(M * i) +: M]), 
                        .ahbl_wait_slv_o(ahbl_wait_s2m_w[(M * i) +: M]), 
                        .ahbl_addr_stall_o(ahbl_addr_stall_w[(M * i) +: M]), 
                        // Inputs
                    .ahbl_hclk_i(ahbl_hclk_i), 
                        .ahbl_hresetn_i(ahbl_hresetn_i), 
                        .ahbl_hsel_slv_i(ahbl_arb_m2s_hsel[(M * i) +: M]), 
                        .ahbl_haddr_slv_i(ahbl_arb_m2s_haddr[((M * AW) * i) +: (M * AW)]), 
                        .ahbl_hburst_slv_i(ahbl_arb_m2s_hburst[((M * 3) * i) +: (M * 3)]), 
                        .ahbl_hsize_slv_i(ahbl_arb_m2s_hsize[((M * 3) * i) +: (M * 3)]), 
                        .ahbl_hmastlock_slv_i(ahbl_arb_m2s_hmastlock[(M * i) +: M]), 
                        .ahbl_hprot_slv_i(ahbl_arb_m2s_hprot[((M * 4) * i) +: (M * 4)]), 
                        .ahbl_htrans_slv_i(ahbl_arb_m2s_htrans[((M * 2) * i) +: (M * 2)]), 
                        .ahbl_hwdata_slv_i(ahbl_arb_m2s_hwdata[((M * DW) * i) +: (M * DW)]), 
                        .ahbl_hwrite_slv_i(ahbl_arb_m2s_hwrite[(M * i) +: M]), 
                        .ahbl_hready_slv_i(ahbl_arb_m2s_hready[(M * i) +: M]), 
                        .ahbl_hreadyout_mstr_i(ahbl_hreadyout_mstr_i[i]), 
                        .ahbl_hresp_mstr_i(ahbl_hresp_mstr_i[i]), 
                        .ahbl_hrdata_mstr_i(ahbl_hrdata_mstr_i[(DW * i) +: DW])) ; 
            // for (i = 0; i < N; i = i + 1)
        end
    endgenerate
    // ------------------------------------------------------------------------------
    // Function Definition
    // ------------------------------------------------------------------------------
    function integer clog2( 
        input integer depth )  ; 
        begin
            if ((depth == 0)) 
                clog2 = 1 ;
            else
                for (clog2 = 0 ; (depth > 0) ; clog2 = (clog2 + 1))
                    depth = (depth >> 1) ;
        end
    endfunction
endmodule



`timescale 1ns/1ps
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS         
// Project               : 
// File                  : lscc_ahbl_decoder.v
// Title                 : 
// Dependencies          : 1.
//                       : 2.
// Description           : 
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             : 
// Mod. Date             : 
// Changes Made          : Initial release.
// =============================================================================
module ahbl0_ipgen_lscc_ahbl_decoder #(parameter F = 8, 
        parameter M_ADDR_WIDTH = 32, 
        parameter FULL_DECODE_EN = 1, 
        parameter TOTAL_SLAVE_CNT = 32, 
        parameter S0_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S0_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S0_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S1_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S1_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S1_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S2_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S2_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S2_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S3_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S3_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S3_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S4_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S4_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S4_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S5_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S5_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S5_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S6_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S6_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S6_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S7_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S7_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S7_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S8_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S8_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S8_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S9_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S9_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S9_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S10_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S10_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S10_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S11_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S11_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S11_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S12_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S12_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S12_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S13_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S13_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S13_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S14_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S14_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S14_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S15_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S15_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S15_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S16_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S16_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S16_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S17_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S17_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S17_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S18_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S18_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S18_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S19_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S19_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S19_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S20_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S20_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S20_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S21_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S21_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S21_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S22_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S22_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S22_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S23_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S23_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S23_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S24_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S24_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S24_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S25_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S25_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S25_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S26_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S26_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S26_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S27_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S27_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S27_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S28_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S28_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S28_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S29_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S29_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S29_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S30_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S30_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S30_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}, 
        parameter S31_FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] S31_BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] S31_ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}) (
    // -----------------------------------------------------------------------------
    // Module Parameters
    // -----------------------------------------------------------------------------
    //parameter                         K               = 32,    // Max Address width
    // Max Fragment count
    // ------------------------------------------------------------------------------
    // Input/Output Ports
    // ------------------------------------------------------------------------------
    input enable_i, 
    input [(M_ADDR_WIDTH - 1):10] ahbl_haddr_i, 
    output wire [(TOTAL_SLAVE_CNT - 1):0] ahbl_hsel_o, 
    output wire ahbl_hsel_def_o) ;
    // ------------------------------------------------------------------------------
    // Local Parameters
    // ------------------------------------------------------------------------------
    localparam N = TOTAL_SLAVE_CNT ; 
    // Each S*_FRAGMENT_EN is 32 bit since there is no size spec in declaration
    localparam [((N * 32) - 1):0] FRAGMENT_EN = {S31_FRAGMENT_EN,
                S30_FRAGMENT_EN,
                S29_FRAGMENT_EN,
                S28_FRAGMENT_EN,
                S27_FRAGMENT_EN,
                S26_FRAGMENT_EN,
                S25_FRAGMENT_EN,
                S24_FRAGMENT_EN,
                S23_FRAGMENT_EN,
                S22_FRAGMENT_EN,
                S21_FRAGMENT_EN,
                S20_FRAGMENT_EN,
                S19_FRAGMENT_EN,
                S18_FRAGMENT_EN,
                S17_FRAGMENT_EN,
                S16_FRAGMENT_EN,
                S15_FRAGMENT_EN,
                S14_FRAGMENT_EN,
                S13_FRAGMENT_EN,
                S12_FRAGMENT_EN,
                S11_FRAGMENT_EN,
                S10_FRAGMENT_EN,
                S9_FRAGMENT_EN,
                S8_FRAGMENT_EN,
                S7_FRAGMENT_EN,
                S6_FRAGMENT_EN,
                S5_FRAGMENT_EN,
                S4_FRAGMENT_EN,
                S3_FRAGMENT_EN,
                S2_FRAGMENT_EN,
                S1_FRAGMENT_EN,
                S0_FRAGMENT_EN} ; 
    localparam [(((N * F) * 32) - 1):0] BASE_ADDR = {S31_BASE_ADDR,
                S30_BASE_ADDR,
                S29_BASE_ADDR,
                S28_BASE_ADDR,
                S27_BASE_ADDR,
                S26_BASE_ADDR,
                S25_BASE_ADDR,
                S24_BASE_ADDR,
                S23_BASE_ADDR,
                S22_BASE_ADDR,
                S21_BASE_ADDR,
                S20_BASE_ADDR,
                S19_BASE_ADDR,
                S18_BASE_ADDR,
                S17_BASE_ADDR,
                S16_BASE_ADDR,
                S15_BASE_ADDR,
                S14_BASE_ADDR,
                S13_BASE_ADDR,
                S12_BASE_ADDR,
                S11_BASE_ADDR,
                S10_BASE_ADDR,
                S9_BASE_ADDR,
                S8_BASE_ADDR,
                S7_BASE_ADDR,
                S6_BASE_ADDR,
                S5_BASE_ADDR,
                S4_BASE_ADDR,
                S3_BASE_ADDR,
                S2_BASE_ADDR,
                S1_BASE_ADDR,
                S0_BASE_ADDR} ; 
    localparam [(((N * F) * 32) - 1):0] ADDR_RANGE = {S31_ADDR_RANGE,
                S30_ADDR_RANGE,
                S29_ADDR_RANGE,
                S28_ADDR_RANGE,
                S27_ADDR_RANGE,
                S26_ADDR_RANGE,
                S25_ADDR_RANGE,
                S24_ADDR_RANGE,
                S23_ADDR_RANGE,
                S22_ADDR_RANGE,
                S21_ADDR_RANGE,
                S20_ADDR_RANGE,
                S19_ADDR_RANGE,
                S18_ADDR_RANGE,
                S17_ADDR_RANGE,
                S16_ADDR_RANGE,
                S15_ADDR_RANGE,
                S14_ADDR_RANGE,
                S13_ADDR_RANGE,
                S12_ADDR_RANGE,
                S11_ADDR_RANGE,
                S10_ADDR_RANGE,
                S9_ADDR_RANGE,
                S8_ADDR_RANGE,
                S7_ADDR_RANGE,
                S6_ADDR_RANGE,
                S5_ADDR_RANGE,
                S4_ADDR_RANGE,
                S3_ADDR_RANGE,
                S2_ADDR_RANGE,
                S1_ADDR_RANGE,
                S0_ADDR_RANGE} ; 
    // ------------------------------------------------------------------------------
    // Wire Declarations
    // ------------------------------------------------------------------------------
    wire [(TOTAL_SLAVE_CNT - 1):0] hsel ; 
    // ------------------------------------------------------------------------------
    // Assign Statements
    // ------------------------------------------------------------------------------
    assign ahbl_hsel_o = (enable_i ? hsel : {TOTAL_SLAVE_CNT{1'b0}}) ; 
    assign ahbl_hsel_def_o = (enable_i ? ((|hsel) ? 1'b0 : 1'b1) : 1'b0) ; 
    // ------------------------------------------------------------------------------
    // Submodule Instantiations
    // ------------------------------------------------------------------------------
    genvar i ; 
    generate
        for (i = 0;(i < TOTAL_SLAVE_CNT);i = (i + 1))
        begin : genblk1
            ahbl0_ipgen_lscc_ahbl_decoder_prim #(.F(F),
                    .M_ADDR_WIDTH(M_ADDR_WIDTH),
                    .FULL_DECODE_EN(FULL_DECODE_EN),
                    .FRAGMENT_EN(FRAGMENT_EN[(32 * i) +: 32]),
                    .BASE_ADDR(BASE_ADDR[((F * 32) * i) +: (F * 32)]),
                    .ADDR_RANGE(ADDR_RANGE[((F * 32) * i) +: (F * 32)])) u_lscc_ahbl_decoder_sel (//      .K                         (K),
                    .enable_i(enable_i), 
                        .addr_i(ahbl_haddr_i), 
                        .sel_o(hsel[i])) ; 
        end
    endgenerate
endmodule



`timescale 1ns/1ps
// ==============================================================================
// lscc_ahbl_decoder.v
// ==============================================================================
//  `ifndef LSCC_AHBL_DECODER
// ==============================================================================
// AHB-Lite Decoder: Primitive
// ==============================================================================
module ahbl0_ipgen_lscc_ahbl_decoder_prim #(parameter F = 8, 
        parameter M_ADDR_WIDTH = 32, 
        parameter FULL_DECODE_EN = 1, 
        parameter FRAGMENT_EN = 4'd1, 
        parameter [((F * 32) - 1):0] BASE_ADDR = {32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0,
                32'h0}, 
        parameter [((F * 32) - 1):0] ADDR_RANGE = {32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400,
                32'h400}) (
    // -----------------------------------------------------------------------------
    // Module Parameters
    // -----------------------------------------------------------------------------
    //parameter                     K            = 32,
    // ------------------------------------------------------------------------------
    // Input/Output Ports
    // ------------------------------------------------------------------------------
    input enable_i, 
    input [(M_ADDR_WIDTH - 1):10] addr_i, 
    output wire sel_o) ;
    // ------------------------------------------------------------------------------
    // Local Parameters
    // ------------------------------------------------------------------------------
    // ------------------------------------------------------------------------------
    // Wire Declarations
    // ------------------------------------------------------------------------------
    wire [(FRAGMENT_EN - 1):0] sel_w ; 
    // ------------------------------------------------------------------------------
    // Assign Statements
    // ------------------------------------------------------------------------------
    assign sel_o = (|sel_w) ; 
    // ------------------------------------------------------------------------------
    // Generate Blocks
    // ------------------------------------------------------------------------------
    genvar i ; 
    // Slave 0
    generate
        for (i = 0;(i < FRAGMENT_EN);i = (i + 1))
        begin : genblk1
            ahbl0_ipgen_lscc_ahbl_decoder_comp #(.FULL_DECODE_EN(FULL_DECODE_EN),
                    .BASE_ADDR(BASE_ADDR[((32 * (i + 1)) - 1):(32 * i)]),
                    .ADDR_RANGE(ADDR_RANGE[((32 * (i + 1)) - 1):(32 * i)]),
                    .ADDR_WIDTH(M_ADDR_WIDTH)) u_lscc_ahbl_decoder_comp (//      .K                      (K),
                    .enable_i(enable_i), 
                        .addr_i(addr_i), 
                        .sel_o(sel_w[i])) ; 
        end
    endgenerate
endmodule



`timescale 1ns/1ps
// ==============================================================================
// lscc_ahbl_decoder_prim.v
// ==============================================================================
//  `ifndef LSCC_AHBL_DECODER_PRIM
// ==============================================================================
// AHB-Lite Decoder: Comparator
// ==============================================================================
module ahbl0_ipgen_lscc_ahbl_decoder_comp #(parameter FULL_DECODE_EN = 1, 
        parameter BASE_ADDR = 32'h0, 
        parameter ADDR_RANGE = 32'h400, 
        parameter ADDR_WIDTH = 32) (
    // ------------------------------------------------------------------------------
    // Module Parameters
    // ------------------------------------------------------------------------------
    //parameter                     K           = 32,
    // ------------------------------------------------------------------------------
    // Input/Output Ports
    // ------------------------------------------------------------------------------
    input enable_i, 
    input [(ADDR_WIDTH - 1):10] addr_i, 
    output reg sel_o) ;
    // ------------------------------------------------------------------------------
    // Local Parameters
    // ------------------------------------------------------------------------------
    localparam MAX_ADDR = ((BASE_ADDR + ADDR_RANGE) - 1) ; 
    localparam RANGE_WIDTH = ((ADDR_RANGE >= 32'h400) ? clog2((ADDR_RANGE - 1)) : 10) ; 
    // ------------------------------------------------------------------------------
    // Wire Declarations
    // ------------------------------------------------------------------------------
    wire [(ADDR_WIDTH - 1):0] min_addr = BASE_ADDR ; 
    wire match_up_bits ; 
    //wire [ADDR_WIDTH-1:0]         addr     = {K{1'b0}} | {addr_i[ADDR_WIDTH-1:10],{10{1'b0}}};
    // ------------------------------------------------------------------------------
    // Combinatorial Blocks
    // ------------------------------------------------------------------------------
    generate
        if (FULL_DECODE_EN) 
            begin : full_dec
                assign match_up_bits = ((addr_i[(ADDR_WIDTH - 1):10] >= BASE_ADDR[(ADDR_WIDTH - 1):10]) && (addr_i[(ADDR_WIDTH - 1):10] <= MAX_ADDR[(ADDR_WIDTH - 1):10])) ; 
            end
        else
            begin : partial_dec
                if ((ADDR_WIDTH > RANGE_WIDTH)) 
                    begin : addr_gt_range
                        assign match_up_bits = (addr_i[(ADDR_WIDTH - 1):RANGE_WIDTH] == min_addr[(ADDR_WIDTH - 1):RANGE_WIDTH]) ; 
                    end
                else
                    begin : addr_eq_range
                        assign match_up_bits = 1'b1 ; 
                    end
            end
    endgenerate
    always
        @(*)
        begin
            sel_o = (enable_i ? match_up_bits : 1'b0) ;
        end
    //------------------------------------------------------------------------------
    // Function Definition
    //------------------------------------------------------------------------------
    function integer clog2( 
        input integer depth )  ; 
        begin
            if ((depth == 0)) 
                clog2 = 1 ;
            else
                for (clog2 = 0 ; (depth > 0) ; clog2 = (clog2 + 1))
                    depth = (depth >> 1) ;
        end
    endfunction

//
endmodule



`timescale 1ns/1ps
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_default_slv.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
module ahbl0_ipgen_lscc_ahbl_default_slv #(parameter DATA_WIDTH = 32) (
    // -----------------------------------------------------------------------------
    // Module Parameters
    // -----------------------------------------------------------------------------
    // ------------------------------------------------------------------------------
    // Input/Output Ports
    // ------------------------------------------------------------------------------
    input ahbl_hclk_i, 
    input ahbl_hresetn_i, 
    input ahbl_hsel_i, 
    input [1:0] ahbl_htrans_i, 
    output reg ahbl_hready_def_o, 
    output reg ahbl_hresp_def_o, 
    output wire [(DATA_WIDTH - 1):0] ahbl_hrdata_def_o) ;
    // ------------------------------------------------------------------------------
    // Local Parameters
    // ------------------------------------------------------------------------------
    localparam ST_WIDTH = 2 ; 
    localparam ST_RDY = 0 ; 
    localparam ST_ERR0 = 1 ; 
    localparam ST_ERR1 = 2 ; 
    localparam IDLE = 2'b00 ; 
    localparam BUSY = 2'b01 ; 
    localparam NSEQ = 2'b10 ; 
    localparam SEQ = 2'b11 ; 
    // ------------------------------------------------------------------------------
    // Combinatorial Registers
    // ------------------------------------------------------------------------------
    reg [(ST_WIDTH - 1):0] ns_sm ; 
    // ------------------------------------------------------------------------------
    // Sequential Registers3
    // ------------------------------------------------------------------------------
    reg [(ST_WIDTH - 1):0] cs_sm ; 
    // ------------------------------------------------------------------------------
    // Assign Statements
    // ------------------------------------------------------------------------------
    assign ahbl_hrdata_def_o = {DATA_WIDTH{1'b1}} ; 
    // ------------------------------------------------------------------------------
    // Combinatorial Block
    // ------------------------------------------------------------------------------
    always
        @(*)
        begin
            ns_sm = cs_sm ;
            ahbl_hready_def_o = 1'b1 ;
            ahbl_hresp_def_o = 1'b0 ;
            case (cs_sm)
            ST_RDY : 
                begin
                    if (ahbl_hsel_i) 
                        begin
                            ns_sm = (((ahbl_htrans_i == NSEQ) || (ahbl_htrans_i == SEQ)) ? ST_ERR0 : ST_RDY) ;
                        end
                end
            ST_ERR0 : 
                begin
                    //      if (ahbl_hsel_i) begin      
                    ahbl_hready_def_o = 1'b0 ;
                    ahbl_hresp_def_o = 1'b1 ;
                    ns_sm = ST_ERR1 ;
                    //      end
                    //      else begin
                    //        ns_sm  = ST_RDY;
                    //      end
                end
            ST_ERR1 : 
                begin
                    ahbl_hready_def_o = 1'b1 ;
                    ahbl_hresp_def_o = 1'b1 ;
                    ns_sm = (((ahbl_htrans_i == IDLE) || (ahbl_htrans_i == BUSY)) ? ST_RDY : ST_ERR0) ;
                end
            default : 
                begin
                    ns_sm = ST_RDY ;
                end
            endcase // case (cs_sm)
        end
    // ------------------------------------------------------------------------------
    // Sequential Block
    // ------------------------------------------------------------------------------
    always
        @(posedge ahbl_hclk_i or 
            negedge ahbl_hresetn_i)
        begin
            if ((~ahbl_hresetn_i)) 
                begin
                    cs_sm <=  ST_RDY ;
                end
            else
                begin
                    cs_sm <=  ns_sm ;
                end
        end
endmodule



`timescale 1ns/1ps
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_arbiter.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
//`timescale 1ns / 1ps
//==========================================================================
// Module : fair_arb
//==========================================================================
module ahbl0_ipgen_lscc_ahbl_fair_arb #(parameter NUM_REQ = 4, 
        parameter ONEHOTPRIO = 1'b0) (
    //--begin_param--
    //----------------------------
    // Parameters
    //----------------------------
    // number of requestor
    // 1 - use onehot encoding of priority, 0 - binary encoding
    //--end_param--
    //--begin_ports--
    input clk, 
    input rst_n, 
    input [(NUM_REQ - 1):0] req, 
    input [(NUM_REQ - 1):0] done, 
    output wire [(NUM_REQ - 1):0] gnt_nxt, 
    output wire [(NUM_REQ - 1):0] gnt) ;
    //--end_ports--
    function [31:0] clog2 ; 
        input [31:0] value ; 
        reg [31:0] num ; 
        begin
            num = (value - 1) ;
            for (clog2 = 0 ; (num > 0) ; clog2 = (clog2 + 1))
                num = (num >> 1) ;
        end
    endfunction
    //--------------------------------------------------------------------------
    //--- Local Parameters/Defines ---
    //--------------------------------------------------------------------------
    localparam GNTWID = ((NUM_REQ > 2) ? NUM_REQ : 1) ; 
    localparam PRIOWID = (NUM_REQ * NUM_REQ) ; 
    localparam LAST_PRIO = {1'b1,
                {(NUM_REQ - 1){1'b0}}} ; 
    localparam FIRST_PRIO = ((NUM_REQ > 2) ? {{(NUM_REQ - 1){1'b0}},
                1'b1} : 1'b0) ; 
    //--------------------------------------------------------------------------
    //--- Combinational Wire/Reg ---
    //--------------------------------------------------------------------------
    reg set_new_gnt ; 
    reg [(GNTWID - 1):0] new_gnt_sel ; 
    reg busy_nxt ; 
    //--------------------------------------------------------------------------
    //--- Registers ---
    //--------------------------------------------------------------------------
    reg [(GNTWID - 1):0] gnt_r ; 
    reg busy ; 
    reg [(GNTWID - 1):0] gnt_nxt_w ; 
    genvar id ; 
    generate
        if ((NUM_REQ > 2)) 
            begin : gen_arb_gt2_req
                reg [(PRIOWID - 1):0] new_prio ; 
                wire [(PRIOWID - 1):0] default_prio ; 
                reg [(PRIOWID - 1):0] prio ; 
                for (id = 0;(id < NUM_REQ);id = (id + 1))
                begin : genblk1
                    assign default_prio[(id * NUM_REQ) +: NUM_REQ] = (FIRST_PRIO << id) ; 
                end
                assign gnt = gnt_r ; 
                assign gnt_nxt = gnt_nxt_w ; 
                //--------------------------------------------
                //-- Combinatorial block --
                //--------------------------------------------
                always//--always @*--
                    @(*)
                    begin
                        new_prio = calc_new_prio(gnt_r,
                                prio) ;
                        new_gnt_sel = get_new_gnt(req,
                                prio) ;
                    end
                if (ONEHOTPRIO) 
                    begin : gen_onehot_prio
                        //--------------------------------------------
                        //-- Sequential block --
                        //--------------------------------------------
                        always//--always @(posedge clk or negedge rst_n)--
                            @(posedge clk or 
                                negedge rst_n)
                            begin
                                if ((~rst_n)) 
                                    begin
                                        prio <=  default_prio ;
                                        /*AUTORESET*/
                                    end
                                else
                                    begin
                                        if (((|(req & gnt_r)) & (~busy))) 
                                            begin
                                                prio <=  new_prio ;
                                            end
                                    end
                            end
                    end
                else
                    begin : gen_binary_prio
                        // ONEHOTPRIO == 0
                        localparam LOG2NUMREQ = clog2(NUM_REQ) ; 
                        localparam BPRIOWID = (NUM_REQ * LOG2NUMREQ) ; 
                        reg [(BPRIOWID - 1):0] new_prio_bin ; 
                        reg [(BPRIOWID - 1):0] default_prio_bin ; 
                        reg [(BPRIOWID - 1):0] prio_bin ; 
                        //--------------------------------------------
                        //-- Sequential block --
                        //--------------------------------------------
                        always//--always @(posedge clk or negedge rst_n)--
                            @(posedge clk or 
                                negedge rst_n)
                            begin
                                if ((~rst_n)) 
                                    begin
                                        prio_bin <=  default_prio_bin ;
                                        /*AUTORESET*/
                                    end
                                else
                                    begin
                                        if (((|(req & gnt_r)) & (~busy))) 
                                            begin
                                                prio_bin <=  new_prio_bin ;
                                            end
                                    end
                            end
                        for (id = 0;(id < NUM_REQ);id = (id + 1))
                        begin : genblk1
                            //--------------------------------------------
                            //-- Combinatorial block --
                            //--------------------------------------------
                            always//--always @*--
                                @(*)
                                begin
                                    prio[(id * NUM_REQ) +: NUM_REQ] = bin_to_onehot(prio_bin[(id * LOG2NUMREQ) +: LOG2NUMREQ]) ;
                                    default_prio_bin[(id * LOG2NUMREQ) +: LOG2NUMREQ] = onehot_to_bin(default_prio[(id * NUM_REQ) +: NUM_REQ]) ;
                                    new_prio_bin[(id * LOG2NUMREQ) +: LOG2NUMREQ] = onehot_to_bin(new_prio[(id * NUM_REQ) +: NUM_REQ]) ;
                                end
                        end
                        // Convert binary to one-hot
                        function [(NUM_REQ - 1):0] bin_to_onehot ; 
                            input [(LOG2NUMREQ - 1):0] bin_in ; 
                            reg [(NUM_REQ - 1):0] out ; 
                            reg [(NUM_REQ - 1):0] i ; 
                            begin
                                out = {NUM_REQ{1'b0}} ;
                                for (i = 0 ; (i < NUM_REQ) ; i = (i + 1))
                                    begin
                                        out[i] = ((bin_in == i) ? 1'b1 : 1'b0) ;
                                    end
                                bin_to_onehot = out ;
                            end
                        endfunction
                        // Convert one-hot to binary
                        function automatic [(LOG2NUMREQ - 1):0] onehot_to_bin ; 
                            input [(NUM_REQ - 1):0] onehot_in ; 
                            reg [(((NUM_REQ + 1) * LOG2NUMREQ) - 1):0] out ; 
                            reg [(NUM_REQ - 1):0] i ; 
                            begin
                                out = {((NUM_REQ + 1) * LOG2NUMREQ){1'b0}} ;
                                for (i = 0 ; (i < NUM_REQ) ; i = (i + 1))
                                    begin
                                        out[((i + 1) * LOG2NUMREQ) +: LOG2NUMREQ] = (onehot_in[i] ? i : out[(i * LOG2NUMREQ) +: LOG2NUMREQ]) ;
                                    end
                                onehot_to_bin = out[(NUM_REQ * LOG2NUMREQ) +: LOG2NUMREQ] ;
                            end
                        endfunction
                    end
                // Calculate new grant
                function [(NUM_REQ - 1):0] get_new_gnt ; 
                    input [(NUM_REQ - 1):0] curr_req ; 
                    input [(PRIOWID - 1):0] allprio ; 
                    integer i ; 
                    begin
                        for (i = 0 ; (i < NUM_REQ) ; i = (i + 1))
                            begin
                                get_new_gnt[i] = (curr_req[i] & calc_next_gnt(i,
                                        curr_req,
                                        allprio)) ;
                            end
                    end
                endfunction
                // Calculate grant per request
                function automatic calc_next_gnt ; 
                    input [31:0] idx ; 
                    input [(NUM_REQ - 1):0] curr_req ; 
                    input [(PRIOWID - 1):0] allprio ; 
                    reg [(NUM_REQ - 1):0] tmpgnt ; 
                    reg [(NUM_REQ - 1):0] mask_req ; 
                    reg [(NUM_REQ - 1):0] req_is_hprio ; 
                    reg [(NUM_REQ - 1):0] tmp_req_is_hprio ; 
                    integer i, 
                        j, 
                        k ; 
                    begin
                        mask_req = curr_req ;
                        mask_req[idx] = 1'b0 ;
                        tmpgnt = {NUM_REQ{1'b0}} ;
                        tmpgnt[0] = allprio[(idx * NUM_REQ)] ;
                        for (i = 1 ; (i < (NUM_REQ - 1)) ; i = (i + 1))
                            begin
                                req_is_hprio = {NUM_REQ{1'b0}} ;
                                for (j = 0 ; (j < NUM_REQ) ; j = (j + 1))
                                    begin
                                        tmp_req_is_hprio = {NUM_REQ{1'b0}} ;
                                        for (k = 0 ; (k < i) ; k = (k + 1))
                                            begin
                                                tmp_req_is_hprio[k] = (mask_req[j] & prio[((j * NUM_REQ) + k)]) ;
                                            end
                                        req_is_hprio[j] = (|tmp_req_is_hprio) ;
                                    end
                                tmpgnt[i] = (((~|req_is_hprio) & allprio[((idx * NUM_REQ) + i)]) | tmpgnt[(i - 1)]) ;
                            end
                        tmpgnt[(NUM_REQ - 1)] = ((~|mask_req) | tmpgnt[(NUM_REQ - 2)]) ;
                        calc_next_gnt = tmpgnt[(NUM_REQ - 1)] ;
                    end
                endfunction
                // Calculate new priority
                function [(PRIOWID - 1):0] calc_new_prio ; 
                    input [(NUM_REQ - 1):0] gnt ; 
                    input [(PRIOWID - 1):0] allprio ; 
                    reg [(NUM_REQ - 1):0] granted_prio ; 
                    reg [(PRIOWID - 1):0] prio_per_gnt ; 
                    integer i ; 
                    begin
                        prio_per_gnt = {PRIOWID{1'b0}} ;
                        granted_prio = get_granted_prio(gnt,
                                allprio) ;
                        for (i = 0 ; (i < NUM_REQ) ; i = (i + 1))
                            begin
                                prio_per_gnt[(i * NUM_REQ) +: NUM_REQ] = get_prio_per_gnt(gnt[i],
                                        allprio[(i * NUM_REQ) +: NUM_REQ],
                                        granted_prio) ;
                            end
                        calc_new_prio = prio_per_gnt ;
                    end
                endfunction
                // Get the priority tag of the currently granted request index
                function automatic [(NUM_REQ - 1):0] get_granted_prio ; 
                    input [(NUM_REQ - 1):0] gnt ; 
                    input [(PRIOWID - 1):0] allprio ; 
                    reg [((PRIOWID + NUM_REQ) - 1):0] granted_prio ; 
                    integer i ; 
                    begin
                        granted_prio = {(PRIOWID + NUM_REQ){1'b0}} ;
                        for (i = 0 ; (i < NUM_REQ) ; i = (i + 1))
                            begin
                                granted_prio[((i + 1) * NUM_REQ) +: NUM_REQ] = (({NUM_REQ{gnt[i]}} & allprio[(i * NUM_REQ) +: NUM_REQ]) | granted_prio[(i * NUM_REQ) +: NUM_REQ]) ;
                            end
                        get_granted_prio = granted_prio[PRIOWID +: NUM_REQ] ;
                    end
                endfunction
                // Calculate new priority given the current grant
                function automatic [(NUM_REQ - 1):0] get_prio_per_gnt ; 
                    input gnt ; 
                    input [(NUM_REQ - 1):0] curr_prio ; 
                    input [(NUM_REQ - 1):0] granted_prio ; 
                    reg [((PRIOWID + NUM_REQ) - 1):0] next_prio ; 
                    reg ored_granted_prio ; 
                    integer i ; 
                    begin
                        next_prio = {(PRIOWID + NUM_REQ){1'b0}} ;
                        if (gnt) 
                            begin
                                next_prio[PRIOWID +: NUM_REQ] = ({1'b1,
                                        {(NUM_REQ - 1){1'b0}}} | next_prio[(0 * NUM_REQ) +: NUM_REQ]) ;
                            end
                        else
                            begin
                                //if(prio_n_[0]) - first
                                next_prio[(1 * NUM_REQ) +: NUM_REQ] = (({NUM_REQ{curr_prio[0]}} & curr_prio) | next_prio[(0 * NUM_REQ) +: NUM_REQ]) ;
                                //if(prio_n_[1] to prio_n_[NUM_REQ-2]) - middle
                                for (i = 1 ; (i < (NUM_REQ - 1)) ; i = (i + 1))
                                    begin
                                        ored_granted_prio = get_ored_value_from_idx(i,
                                                granted_prio) ;
                                        if (ored_granted_prio) 
                                            next_prio[((i + 1) * NUM_REQ) +: NUM_REQ] = (({NUM_REQ{curr_prio[i]}} & {curr_prio[0],
                                                    curr_prio[(NUM_REQ - 1):1]}) | next_prio[(i * NUM_REQ) +: NUM_REQ]) ;
                                        else
                                            next_prio[((i + 1) * NUM_REQ) +: NUM_REQ] = (({NUM_REQ{curr_prio[i]}} & curr_prio) | next_prio[(i * NUM_REQ) +: NUM_REQ]) ;
                                    end
                                //if(prio_n_[NUM_REQ-1]) - last
                                next_prio[PRIOWID +: NUM_REQ] = (({NUM_REQ{curr_prio[(NUM_REQ - 1)]}} & {curr_prio[0],
                                        curr_prio[(NUM_REQ - 1):1]}) | next_prio[(PRIOWID - NUM_REQ) +: NUM_REQ]) ;
                            end
                        get_prio_per_gnt = next_prio[PRIOWID +: NUM_REQ] ;
                    end
                endfunction
                // Get the ORed value from specified index to 0
                function automatic get_ored_value_from_idx ; 
                    input [31:0] idx ; 
                    input [(NUM_REQ - 1):0] granted_prio ; 
                    reg [(NUM_REQ - 1):0] out ; 
                    integer i ; 
                    begin
                        out = {NUM_REQ{1'b0}} ;
                        for (i = 0 ; (i < idx) ; i = (i + 1))
                            begin
                                out[i] = granted_prio[i] ;
                            end
                        get_ored_value_from_idx = (|out) ;
                    end
                endfunction
            end
        else
            begin : gen_arb_2_req
                // NUM_REQ == 2
                assign gnt[0] = (~gnt_r) ; 
                assign gnt[1] = gnt_r ; 
                //--------------------------------------------
                //-- New grant --
                //--------------------------------------------
                always//--always @*--
                    @(*)
                    begin
                        if (gnt_r) 
                            new_gnt_sel = (req[0] ? 1'b0 : 1'b1) ;
                        else
                            new_gnt_sel = (req[1] ? 1'b1 : 1'b0) ;
                    end
            end
    endgenerate
    //--------------------------------------------
    //-- Arbiter busy --
    //--------------------------------------------
    always//--always @*--
        @(*)
        begin
            busy_nxt = (((|(((~done) & gnt) & req)) & (~busy)) | ((~|(done & gnt)) & busy)) ;
        end
    //--------------------------------------------
    //-- Change the granted port --
    //-- if there is a request which is currently
    // not granted and current grant is done --
    //--------------------------------------------
    always//--always @*--
        @(*)
        begin
            set_new_gnt = (((|(req & (~gnt))) & (~busy_nxt)) | ((|(done & gnt)) & (busy_nxt | busy))) ;
            if (set_new_gnt) 
                gnt_nxt_w = new_gnt_sel ;
            else
                gnt_nxt_w = gnt_r ;
        end
    //--------------------------------------------
    //-- Sequential block --
    //--------------------------------------------
    always//--always @(posedge clk or negedge rst_n)--
        @(posedge clk or 
            negedge rst_n)
        begin
            if ((~rst_n)) 
                begin
                    gnt_r <=  FIRST_PRIO ;
                    /*AUTORESET*/
                    // Beginning of autoreset for uninitialized flops
                    busy <=  {1{1'b0}} ;
                    // End of automatics
                end
            else
                begin
                    busy <=  busy_nxt ;
                    gnt_r <=  gnt_nxt_w ;
                end
        end

//--------------------------------------------------------------------------
//--- Module Instantiation ---
//--------------------------------------------------------------------------
// assertions - for debugging
//--fair_arb--
endmodule



`timescale 1ns/1ps
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_crossbar.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_arbmux.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_arbiter.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
// __RTL_MODULE__FAIR_ARB__
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_arbiter.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
// ==============================================================================
// AHB-Lite Priority Arbiter
// ==============================================================================
//// ==============================================================================
//// AHB-Lite Thermometer Mask
//// ==============================================================================
//`ifndef LSCC_AHBL_THERMO_MASK
//`define LSCC_AHBL_THERMO_MASK
//
//module lscc_ahbl_thermo_mask #
//// -----------------------------------------------------------------------------
//// Module Parameters
//// -----------------------------------------------------------------------------
//(
//parameter                     M = 32
//)
//// ------------------------------------------------------------------------------
//// Input/Output Ports
//// ------------------------------------------------------------------------------
//(
//input [M-1:0]                 vector_i,
//output reg [M-1:0]            mask_o
//);
//
//// ------------------------------------------------------------------------------
//// Combinatorial Block
//// ------------------------------------------------------------------------------
//always @(*) begin
//  // Outputs 1 at the first set bit and all less significant (leftmost) bits.
//  // Outputs 0 for all more significant (rightmost) bits.
//  // Outputs all 1's if no bit set.
//
//  mask_o = vector_i ^ (vector_i - 1);
//
//  // Invert mask to instead mask-off the set bit and the less significant bits
//  // Don't invert mask if no bit set (don't want an all-zero mask)
//
//  mask_o = (vector_i == {M{1'b0}}) ? mask_o : ~mask_o;
//
//  // Re-add set bit, so it and the more significant (rightmost) bits pass.
//
//  // mask_o = mask_o | vector_i;
//end
//
//endmodule
//==============================================================================
// lscc_ahbl_thermo_mask.v
// Local Variables:
// verilog-library-directories:("." "../../ahbl_default_slv/rtl/")
// End:
//==============================================================================
//`endif
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_bus.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS         
// Project               : 
// File                  : lscc_ahbl_decoder.v
// Title                 : 
// Dependencies          : 1.
//                       : 2.
// Description           : 
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             : 
// Mod. Date             : 
// Changes Made          : Initial release.
// =============================================================================
//  `ifndef LSCC_AHBL_DECODER
// ==============================================================================
// AHB-Lite Decoder: Primitive
// ==============================================================================
//  `ifndef LSCC_AHBL_DECODER_PRIM
// ==============================================================================
// AHB-Lite Decoder: Comparator
// ==============================================================================
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS         
// Project               : 
// File                  : lscc_ahbl_multiplexor.v
// Title                 : 
// Dependencies          : 1.
//                       : 2.
// Description           : 
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             : 
// Mod. Date             : 
// Changes Made          : Initial release.
// =============================================================================
module ahbl0_ipgen_lscc_ahbl_multiplexor #(parameter M_ADDR_WIDTH = 32, 
        parameter DATA_WIDTH = 32, 
        parameter TOTAL_SLAVE_CNT = 32, 
        parameter OUTREG_EN = 0) (
    // -----------------------------------------------------------------------------
    // Module Parameters
    // -----------------------------------------------------------------------------
    //parameter                                     K               = 32,
    // ------------------------------------------------------------------------------
    // Input/Output Ports
    // ------------------------------------------------------------------------------
    input ahbl_hclk_i, 
    input ahbl_hresetn_i, 
    // ----------------------
    // From AHB-Lite Decoder
    // ----------------------
    input [(TOTAL_SLAVE_CNT - 1):0] ahbl_hsel_dec_i, 
    // ----------------------------------------
    // AHB-Lite Master Interface (to/from master)
    // ----------------------------------------
    input ahbl_hsel_slv_i, 
    input [(M_ADDR_WIDTH - 1):0] ahbl_haddr_slv_i, 
    input [2:0] ahbl_hburst_slv_i, 
    input [2:0] ahbl_hsize_slv_i, 
    input ahbl_hmastlock_slv_i, 
    input [3:0] ahbl_hprot_slv_i, 
    input [1:0] ahbl_htrans_slv_i, 
    input [(DATA_WIDTH - 1):0] ahbl_hwdata_slv_i, 
    input ahbl_hwrite_slv_i, 
    input ahbl_hready_slv_i, 
    output ahbl_hreadyout_slv_o, 
    output ahbl_hresp_slv_o, 
    output [(DATA_WIDTH - 1):0] ahbl_hrdata_slv_o, 
    // -----------------------------------------
    // AHB-Lite Slave Interface (to/from slave)
    // -----------------------------------------
    output reg [(TOTAL_SLAVE_CNT - 1):0] ahbl_hsel_mstr_o, 
    output reg [((TOTAL_SLAVE_CNT * M_ADDR_WIDTH) - 1):0] ahbl_haddr_mstr_o, 
    output reg [((TOTAL_SLAVE_CNT * 3) - 1):0] ahbl_hburst_mstr_o, 
    output reg [((TOTAL_SLAVE_CNT * 3) - 1):0] ahbl_hsize_mstr_o, 
    output reg [(TOTAL_SLAVE_CNT - 1):0] ahbl_hmastlock_mstr_o, 
    output reg [((TOTAL_SLAVE_CNT * 4) - 1):0] ahbl_hprot_mstr_o, 
    output reg [((TOTAL_SLAVE_CNT * 2) - 1):0] ahbl_htrans_mstr_o, 
    output reg [((TOTAL_SLAVE_CNT * DATA_WIDTH) - 1):0] ahbl_hwdata_mstr_o, 
    output reg [(TOTAL_SLAVE_CNT - 1):0] ahbl_hwrite_mstr_o, 
    output reg [(TOTAL_SLAVE_CNT - 1):0] ahbl_hready_mstr_o, 
    input [(TOTAL_SLAVE_CNT - 1):0] ahbl_hreadyout_mstr_i, 
    input [(TOTAL_SLAVE_CNT - 1):0] ahbl_hresp_mstr_i, 
    input [((TOTAL_SLAVE_CNT * DATA_WIDTH) - 1):0] ahbl_hrdata_mstr_i, 
    // -------------------------------------------------
    // AHB-Lite DEFAULT Slave Interface (to/from slave)
    // -------------------------------------------------
    input ahbl_hsel_def_mstr_i, 
    input ahbl_hready_def_mstr_i, 
    input ahbl_hresp_def_mstr_i, 
    input [(DATA_WIDTH - 1):0] ahbl_hrdata_def_mstr_i) ;
    // ------------------------------------------------------------------------------
    // Local Parameters
    // ------------------------------------------------------------------------------
    //localparam                                    SEL_WIDTH = clog2(TOTAL_SLAVE_CNT);
    // ------------------------------------------------------------------------------
    // Register Declarations
    // ------------------------------------------------------------------------------
    reg [(TOTAL_SLAVE_CNT - 1):0] hsel_dec_Q ; 
    reg [(TOTAL_SLAVE_CNT - 1):0] ahbl_hsel_dec_r ; 
    reg hsel_def_Q ; 
    reg active_tx_r ; 
    reg hready_data_phase ; 
    reg hready_internal ; 
    reg hready ; 
    reg hresp ; 
    reg [(DATA_WIDTH - 1):0] hrdata ; 
    reg [(((TOTAL_SLAVE_CNT + 1) * DATA_WIDTH) - 1):0] tmp_data ; 
    //reg  [SEL_WIDTH-1:0]                          msel;
    //reg  [SEL_WIDTH-1:0]                          ssel_r;
    //reg  [SEL_WIDTH-1:0]                          ssel_nxt;
    wire hreadyout ; 
    wire hready_mstr_w ; 
    //wire [TOTAL_SLAVE_CNT:0]                      ahbl_hreadyout_w;
    //wire [TOTAL_SLAVE_CNT:0]                      ahbl_hresp_w;
    //wire [(TOTAL_SLAVE_CNT+1)*DATA_WIDTH-1:0]     ahbl_hrdata_w;
    // ------------------------------------------------------------------------------
    // Assign Statements
    // ------------------------------------------------------------------------------
    //assign ahbl_hreadyout_w = {ahbl_hready_def_mstr_i,ahbl_hreadyout_mstr_i};
    //assign ahbl_hresp_w     = {ahbl_hresp_def_mstr_i,ahbl_hresp_mstr_i};
    //assign ahbl_hrdata_w    = {ahbl_hrdata_def_mstr_i,ahbl_hrdata_mstr_i};
    // ------------------------------------------------------------------------------
    // Generate Blocks
    // ------------------------------------------------------------------------------
    integer i, 
        j ; 
    // ----------
    // To Master
    // ----------
    generate
        if ((OUTREG_EN == 0)) 
            begin : noreg
                always
                    @(*)
                    begin
                        tmp_data = {((TOTAL_SLAVE_CNT + 1) * DATA_WIDTH){1'b0}} ;
                        hready = (|(ahbl_hsel_dec_r & ahbl_hreadyout_mstr_i)) ;
                        hresp = (|(ahbl_hsel_dec_r & ahbl_hresp_mstr_i)) ;
                        for (j = 0 ; (j < TOTAL_SLAVE_CNT) ; j = (j + 1))
                            begin
                                tmp_data[(DATA_WIDTH * (j + 1)) +: DATA_WIDTH] = (({DATA_WIDTH{ahbl_hsel_dec_r[j]}} & ahbl_hrdata_mstr_i[(DATA_WIDTH * j) +: DATA_WIDTH]) | tmp_data[(DATA_WIDTH * j) +: DATA_WIDTH]) ;
                            end
                        hrdata = tmp_data[(DATA_WIDTH * TOTAL_SLAVE_CNT) +: DATA_WIDTH] ;
                    end
            end
        else
            begin : outreg
            end
    endgenerate
    assign ahbl_hreadyout_slv_o = (hsel_def_Q ? ahbl_hready_def_mstr_i : hready) ; 
    assign ahbl_hresp_slv_o = (hsel_def_Q ? ahbl_hresp_def_mstr_i : hresp) ; 
    assign ahbl_hrdata_slv_o = (hsel_def_Q ? ahbl_hrdata_def_mstr_i : hrdata) ; 
    assign hready_mstr_w = (ahbl_hreadyout_slv_o | (~active_tx_r)) ; 
    generate
        always
            @(*)
            begin
                // HREADY output of master is connected to all slave
                ahbl_hready_mstr_o = {TOTAL_SLAVE_CNT{hready_mstr_w}} ;
            end
        if ((OUTREG_EN == 0)) 
            begin : outreg_mstr_off
                always// always @ *
                    @(*)
                    begin
                        ahbl_hsel_mstr_o = ahbl_hsel_dec_i ;
                        for (i = 0 ; (i < TOTAL_SLAVE_CNT) ; i = (i + 1))// for (i = 0; i < TOTAL_SLAVE_CNT; i = i + 1) 
                            begin
                                ahbl_haddr_mstr_o[(M_ADDR_WIDTH * i) +: M_ADDR_WIDTH] = ahbl_haddr_slv_i ;
                                ahbl_hburst_mstr_o[(3 * i) +: 3] = ahbl_hburst_slv_i ;
                                ahbl_hsize_mstr_o[(3 * i) +: 3] = ahbl_hsize_slv_i ;
                                ahbl_hmastlock_mstr_o[i] = ahbl_hmastlock_slv_i ;
                                ahbl_hprot_mstr_o[(4 * i) +: 4] = ahbl_hprot_slv_i ;
                                ahbl_hwrite_mstr_o[i] = ahbl_hwrite_slv_i ;
                                ahbl_hwdata_mstr_o[(DATA_WIDTH * i) +: DATA_WIDTH] = ahbl_hwdata_slv_i ;
                                // Only HTRANS is set to 0 when not in use
                                if ((ahbl_hsel_dec_i[i] && (~ahbl_hsel_def_mstr_i))) 
                                //        if (hsel_dec_Q[i]) 
                                //          ahbl_hwdata_mstr_o[(DATA_WIDTH*i)+:DATA_WIDTH]  = ahbl_hwdata_slv_i;
                                //        else
                                //          ahbl_hwdata_mstr_o[(DATA_WIDTH*i)+:DATA_WIDTH]  = 0;
                                    // ~hsel_def_Q)
                                    ahbl_htrans_mstr_o[(2 * i) +: 2] = ahbl_htrans_slv_i ;
                                else
                                    ahbl_htrans_mstr_o[(2 * i) +: 2] = 2'b00 ;
                            end
                    end
            end
        else
            begin : outreg_mstr_on
            end
    endgenerate
    // ---------
    // To Slave
    // ---------
    always
        @(*)
        begin
            //  msel  = TOTAL_SLAVE_CNT;
            //  for (i = 0; i < TOTAL_SLAVE_CNT; i = i + 1) begin
            //    if (ahbl_hsel_dec_i == (1 << i)) begin
            //      msel = i;
            //    end 
            //  end
            //  if (ahbl_hsel_slv_i && (ahbl_htrans_slv_i != 2'b00))
            //    ssel_nxt = msel;
            //  else 
            //    ssel_nxt = ssel_r;
            //  hready_addr_phase = ahbl_hreadyout_mstr_i[ssel_nxt];
            //  hready_data_phase = ahbl_hreadyout_mstr_i[ssel_r];
            hready_data_phase = (|(ahbl_hreadyout_mstr_i & ahbl_hsel_dec_r)) ;
            // Note: hready_internal is needed for Multi-layer interconnect because ArbMux negates HREADY
            // for not granted master, multiplexor need to identify the actual ready condition for internal use
            if (active_tx_r) 
                hready_internal = hready_data_phase ;
            else
                hready_internal = 1'b1 ;
        end
    // ------------------------------------------------------------------------------
    // Sequential Blocks
    // ------------------------------------------------------------------------------
    always
        @(posedge ahbl_hclk_i or 
            negedge ahbl_hresetn_i)
        begin
            if ((~ahbl_hresetn_i)) 
                begin
                    //    hsel_dec_Q      <= {TOTAL_SLAVE_CNT{1'b0}};
                    ahbl_hsel_dec_r <=  {TOTAL_SLAVE_CNT{1'b0}} ;
                    active_tx_r <=  1'b0 ;
                    hsel_def_Q <=  1'b1 ;
                end
            else
                begin
                    if (hready_internal) 
                        begin
                            if (((ahbl_hready_slv_i && ahbl_hsel_slv_i) && (ahbl_htrans_slv_i == 2'b10))) 
                                active_tx_r <=  1'b1 ;
                            else
                                if ((ahbl_htrans_slv_i == 2'b00)) 
                                    active_tx_r <=  1'b0 ;
                            //      hsel_dec_Q <= ahbl_hsel_dec_i;
                            if ((ahbl_hsel_slv_i && (ahbl_htrans_slv_i != 2'b00))) 
                                begin
                                    ahbl_hsel_dec_r <=  ahbl_hsel_dec_i ;
                                    hsel_def_Q <=  ahbl_hsel_def_mstr_i ;
                                end
                        end
                end
        end

//------------------------------------------------------------------------------
// Function Definition
//------------------------------------------------------------------------------
//function integer clog2 (input integer depth);
//  begin
//    if (depth == 0)
//      clog2 = 1;
//    else
//      for (clog2 = 0; depth > 0;  clog2 = clog2 + 1)
//        depth = depth >> 1;
//  end
//endfunction
endmodule



`timescale 1ns/1ps
// ==============================================================================
// AHB-Lite Multiplexor
// ==============================================================================
//  `ifndef LSCC_AHBL_MULTIPLEXOR
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_default_slv.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_input_stage.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
module ahbl0_ipgen_lscc_ahbl_input_stage #(parameter M_ADDR_WIDTH = 32) (
    // -----------------------------------------------------------------------------
    // Module Parameters
    // -----------------------------------------------------------------------------
    // ------------------------------------------------------------------------------
    // Input/Output Ports
    // ------------------------------------------------------------------------------
    input ahbl_hclk_i, 
    input ahbl_hresetn_i, 
    // ----------------------------------------
    // AHB-Lite Arbiter-Mux
    // ----------------------------------------
    input ahbl_arb_en_i, 
    input ahbl_start_i, 
    input ahbl_grant_i, 
    input ahbl_wait_i, 
    input ahbl_addr_stall_i, 
    // ----------------------------------------
    // AHB-Lite Master Interface (to/from master)
    // ----------------------------------------
    output reg ahbl_hreadyout_slv_o, 
    input ahbl_hready_slv_i, 
    input [1:0] ahbl_htrans_slv_i, 
    input [(M_ADDR_WIDTH - 1):0] ahbl_haddr_slv_i, 
    input [2:0] ahbl_hburst_slv_i, 
    input [2:0] ahbl_hsize_slv_i, 
    input ahbl_hmastlock_slv_i, 
    input [3:0] ahbl_hprot_slv_i, 
    input ahbl_hwrite_slv_i, 
    input ahbl_hsel_slv_i, 
    input ahbl_hresp_slv_i, 
    // -----------------------------------------
    // AHB-Lite Slave Interface (to/from slave)
    // -----------------------------------------
    input ahbl_hreadyout_slv_i, 
    output reg ahbl_hready_slv_o, 
    output reg [1:0] ahbl_htrans_slv_o, 
    output reg [(M_ADDR_WIDTH - 1):0] ahbl_haddr_slv_o, 
    output reg [2:0] ahbl_hburst_slv_o, 
    output reg [2:0] ahbl_hsize_slv_o, 
    output reg ahbl_hmastlock_slv_o, 
    output reg [3:0] ahbl_hprot_slv_o, 
    output reg ahbl_hwrite_slv_o, 
    output reg ahbl_hsel_slv_o) ;
    // ------------------------------------------------------------------------------
    // Local Parameters
    // ------------------------------------------------------------------------------
    localparam IDLE = 2'b00 ; 
    localparam BUSY = 2'b01 ; 
    localparam NSEQ = 2'b10 ; 
    localparam SEQ = 2'b11 ; 
    // ------------------------------------------------------------------------------
    // Register Declarations
    // ------------------------------------------------------------------------------
    reg [1:0] reg_htrans_slv ; 
    reg [(M_ADDR_WIDTH - 1):0] reg_haddr_slv ; 
    reg [2:0] reg_hburst_slv ; 
    reg [2:0] reg_hsize_slv ; 
    reg reg_hmastlock_slv ; 
    reg [3:0] reg_hprot_slv ; 
    reg reg_hwrite_slv ; 
    reg reg_hsel_slv ; 
    reg regs_has_data_r ; 
    reg regs_has_data_2_r ; 
    reg hresp_d1_r ; 
    reg hresp_d2_r ; 
    reg bus_is_idle_r ; 
    //reg                           prev_stall_r;
    // ------------------------------------------------------------------------------
    // Wire Declarations
    // ------------------------------------------------------------------------------
    //wire stall_pulse_w;
    // ------------------------------------------------------------------------------
    // Assign Statements
    // ------------------------------------------------------------------------------
    // ------------------------------------------------------------------------------
    // Combinatorial Block
    // ------------------------------------------------------------------------------
    always
        @(*)
        begin
            ahbl_htrans_slv_o = (regs_has_data_r ? reg_htrans_slv : ahbl_htrans_slv_i) ;
            ahbl_haddr_slv_o = (regs_has_data_r ? reg_haddr_slv : ahbl_haddr_slv_i) ;
            ahbl_hburst_slv_o = (regs_has_data_r ? reg_hburst_slv : ahbl_hburst_slv_i) ;
            ahbl_hsize_slv_o = (regs_has_data_r ? reg_hsize_slv : ahbl_hsize_slv_i) ;
            ahbl_hmastlock_slv_o = (regs_has_data_r ? reg_hmastlock_slv : ahbl_hmastlock_slv_i) ;
            ahbl_hprot_slv_o = (regs_has_data_r ? reg_hprot_slv : ahbl_hprot_slv_i) ;
            ahbl_hwrite_slv_o = (regs_has_data_r ? reg_hwrite_slv : ahbl_hwrite_slv_i) ;
            ahbl_hsel_slv_o = (regs_has_data_r ? reg_hsel_slv : ahbl_hsel_slv_i) ;
            // HREADY input going to Bus should be asserted when input has been buffered
            ahbl_hready_slv_o = (regs_has_data_2_r | ahbl_hready_slv_i) ;
            // HREADYOUT going to External master
            if (((~regs_has_data_2_r) & (~bus_is_idle_r))) 
            //  end
                // input stage is empty and Bus is active
                ahbl_hreadyout_slv_o = ahbl_hreadyout_slv_i ;
            else
                if (((~regs_has_data_2_r) & bus_is_idle_r)) 
                    ahbl_hreadyout_slv_o = 1 ;
                else
                    ahbl_hreadyout_slv_o = ((~hresp_d2_r) & hresp_d1_r) ;
        end
    wire slave_side_ready_w ; 
    wire master_side_ready_w ; 
    assign slave_side_ready_w = (ahbl_hready_slv_o & ahbl_hreadyout_slv_i) ; 
    assign master_side_ready_w = (ahbl_hready_slv_i & ahbl_hreadyout_slv_o) ; 
    // ------------------------------------------------------------------------------
    // Sequential Block
    // ------------------------------------------------------------------------------
    always
        @(posedge ahbl_hclk_i or 
            negedge ahbl_hresetn_i)
        begin
            if ((!ahbl_hresetn_i)) 
                begin
                    regs_has_data_r <=  1'b0 ;
                    regs_has_data_2_r <=  1'b0 ;
                    reg_htrans_slv <=  0 ;
                    reg_haddr_slv <=  0 ;
                    reg_hburst_slv <=  0 ;
                    reg_hsize_slv <=  0 ;
                    reg_hmastlock_slv <=  0 ;
                    reg_hprot_slv <=  0 ;
                    reg_hwrite_slv <=  0 ;
                    reg_hsel_slv <=  0 ;
                    hresp_d1_r <=  0 ;
                    hresp_d2_r <=  0 ;
                    bus_is_idle_r <=  1 ;
                    //    prev_stall_r      <= 0;
                end
            else
                begin
                    //    prev_stall_r      <= ahbl_addr_stall_i;
                    if (master_side_ready_w) 
                        // Ready in Master point-of-view
                        if ((ahbl_htrans_slv_i == 2'b00)) 
                            bus_is_idle_r <=  1'b1 ;
                        else
                            if (((ahbl_htrans_slv_i == 2'b10) && ahbl_hsel_slv_i)) 
                                bus_is_idle_r <=  1'b0 ;
                    hresp_d1_r <=  ahbl_hresp_slv_i ;
                    hresp_d2_r <=  hresp_d1_r ;
                    //if (~regs_has_data_r && ahbl_addr_stall_i && master_side_ready_w && (ahbl_htrans_slv_i != 2'b00)) begin
                    if (((((~regs_has_data_r) && ahbl_addr_stall_i) && master_side_ready_w) && (ahbl_htrans_slv_i != 2'b00))) 
                        begin
                            regs_has_data_r <=  1'b1 ;
                            regs_has_data_2_r <=  1'b1 ;
                            reg_htrans_slv <=  ahbl_htrans_slv_i ;
                            reg_haddr_slv <=  ahbl_haddr_slv_i ;
                            reg_hburst_slv <=  ahbl_hburst_slv_i ;
                            reg_hsize_slv <=  ahbl_hsize_slv_i ;
                            reg_hmastlock_slv <=  ahbl_hmastlock_slv_i ;
                            reg_hprot_slv <=  ahbl_hprot_slv_i ;
                            reg_hwrite_slv <=  ahbl_hwrite_slv_i ;
                            reg_hsel_slv <=  ahbl_hsel_slv_i ;
                        end
                    else
                        if (slave_side_ready_w) 
                            begin
                                // Ready in Slave point-of-view
                                regs_has_data_2_r <=  1'b0 ;
                                regs_has_data_r <=  1'b0 ;
                            end
                end
        end

// lscc_ahbl_input_stage
endmodule



`timescale 1ns/1ps
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_interconnect.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_crossbar.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_arbmux.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_arbiter.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
// __RTL_MODULE__FAIR_ARB__
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_arbiter.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
// ==============================================================================
// AHB-Lite Priority Arbiter
// ==============================================================================
//// ==============================================================================
//// AHB-Lite Thermometer Mask
//// ==============================================================================
//`ifndef LSCC_AHBL_THERMO_MASK
//`define LSCC_AHBL_THERMO_MASK
//
//module lscc_ahbl_thermo_mask #
//// -----------------------------------------------------------------------------
//// Module Parameters
//// -----------------------------------------------------------------------------
//(
//parameter                     M = 32
//)
//// ------------------------------------------------------------------------------
//// Input/Output Ports
//// ------------------------------------------------------------------------------
//(
//input [M-1:0]                 vector_i,
//output reg [M-1:0]            mask_o
//);
//
//// ------------------------------------------------------------------------------
//// Combinatorial Block
//// ------------------------------------------------------------------------------
//always @(*) begin
//  // Outputs 1 at the first set bit and all less significant (leftmost) bits.
//  // Outputs 0 for all more significant (rightmost) bits.
//  // Outputs all 1's if no bit set.
//
//  mask_o = vector_i ^ (vector_i - 1);
//
//  // Invert mask to instead mask-off the set bit and the less significant bits
//  // Don't invert mask if no bit set (don't want an all-zero mask)
//
//  mask_o = (vector_i == {M{1'b0}}) ? mask_o : ~mask_o;
//
//  // Re-add set bit, so it and the more significant (rightmost) bits pass.
//
//  // mask_o = mask_o | vector_i;
//end
//
//endmodule
//==============================================================================
// lscc_ahbl_thermo_mask.v
// Local Variables:
// verilog-library-directories:("." "../../ahbl_default_slv/rtl/")
// End:
//==============================================================================
//`endif
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_bus.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS         
// Project               : 
// File                  : lscc_ahbl_decoder.v
// Title                 : 
// Dependencies          : 1.
//                       : 2.
// Description           : 
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             : 
// Mod. Date             : 
// Changes Made          : Initial release.
// =============================================================================
//  `ifndef LSCC_AHBL_DECODER
// ==============================================================================
// AHB-Lite Decoder: Primitive
// ==============================================================================
//  `ifndef LSCC_AHBL_DECODER_PRIM
// ==============================================================================
// AHB-Lite Decoder: Comparator
// ==============================================================================
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS         
// Project               : 
// File                  : lscc_ahbl_multiplexor.v
// Title                 : 
// Dependencies          : 1.
//                       : 2.
// Description           : 
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             : 
// Mod. Date             : 
// Changes Made          : Initial release.
// =============================================================================
//  `ifndef LSCC_AHBL_MULTIPLEXOR
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_default_slv.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
/* >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

       LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE'S REQUIREMENTS, OR THAT LICENSEE'S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED.  LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM.  LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.  IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE'S SOLE LIABILITY, AND LICENSEE'S SOLE REMEDY, IS SET FORTH ABOVE.  LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER'S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.

     ------------------------------------------------------------------
 */
//
// =============================================================================
//                         FILE DETAILS
// Project               :
// File                  : lscc_ahbl_input_stage.v
// Title                 :
// Dependencies          : 1.
//                       : 2.
// Description           :
// =============================================================================
//                        REVISION HISTORY
// Version               : 1.0.0
// Author(s)             :
// Mod. Date             :
// Changes Made          : Initial release.
// =============================================================================
module ahbl0_ipgen_lscc_ahbl_interconnect #(parameter F = 8, 
        parameter TOTAL_MASTER_CNT = 8, 
        parameter TOTAL_SLAVE_CNT = 8, 
        parameter M_ADDR_WIDTH = 32, 
        parameter FULL_DECODE_EN = 1, 
        parameter M_PRIO_WIDTH = clog2(TOTAL_MASTER_CNT), 
        parameter DATA_WIDTH = 32, 
        parameter OUTREG_EN = 0, 
        parameter FAMILY = "LIFCL", 
        parameter S0_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S0_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S0_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S0_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S0_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S0_MAX_BURST_SIZE = 9'd0, 
        parameter S1_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S1_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S1_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S1_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S1_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S1_MAX_BURST_SIZE = 9'd0, 
        parameter S2_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S2_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S2_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S2_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S2_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S2_MAX_BURST_SIZE = 9'd0, 
        parameter S3_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S3_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S3_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S3_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S3_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S3_MAX_BURST_SIZE = 9'd0, 
        parameter S4_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S4_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S4_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S4_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S4_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S4_MAX_BURST_SIZE = 9'd0, 
        parameter S5_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S5_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S5_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S5_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S5_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S5_MAX_BURST_SIZE = 9'd0, 
        parameter S6_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S6_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S6_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S6_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S6_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S6_MAX_BURST_SIZE = 9'd0, 
        parameter S7_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S7_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S7_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S7_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S7_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S7_MAX_BURST_SIZE = 9'd0, 
        parameter S8_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S8_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S8_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S8_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S8_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S8_MAX_BURST_SIZE = 9'd0, 
        parameter S9_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S9_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S9_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S9_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S9_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S9_MAX_BURST_SIZE = 9'd0, 
        parameter S10_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S10_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S10_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S10_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S10_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S10_MAX_BURST_SIZE = 9'd0, 
        parameter S11_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S11_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S11_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S11_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S11_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S11_MAX_BURST_SIZE = 9'd0, 
        parameter S12_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S12_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S12_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S12_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S12_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S12_MAX_BURST_SIZE = 9'd0, 
        parameter S13_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S13_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S13_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S13_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S13_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S13_MAX_BURST_SIZE = 9'd0, 
        parameter S14_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S14_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S14_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S14_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S14_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S14_MAX_BURST_SIZE = 9'd0, 
        parameter S15_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S15_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S15_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S15_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S15_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S15_MAX_BURST_SIZE = 9'd0, 
        parameter S16_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S16_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S16_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S16_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S16_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S16_MAX_BURST_SIZE = 9'd0, 
        parameter S17_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S17_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S17_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S17_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S17_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S17_MAX_BURST_SIZE = 9'd0, 
        parameter S18_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S18_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S18_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S18_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S18_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S18_MAX_BURST_SIZE = 9'd0, 
        parameter S19_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S19_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S19_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S19_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S19_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S19_MAX_BURST_SIZE = 9'd0, 
        parameter S20_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S20_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S20_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S20_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S20_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S20_MAX_BURST_SIZE = 9'd0, 
        parameter S21_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S21_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S21_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S21_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S21_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S21_MAX_BURST_SIZE = 9'd0, 
        parameter S22_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S22_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S22_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S22_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S22_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S22_MAX_BURST_SIZE = 9'd0, 
        parameter S23_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S23_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S23_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S23_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S23_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S23_MAX_BURST_SIZE = 9'd0, 
        parameter S24_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S24_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S24_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S24_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S24_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S24_MAX_BURST_SIZE = 9'd0, 
        parameter S25_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S25_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S25_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S25_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S25_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S25_MAX_BURST_SIZE = 9'd0, 
        parameter S26_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S26_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S26_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S26_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S26_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S26_MAX_BURST_SIZE = 9'd0, 
        parameter S27_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S27_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S27_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S27_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S27_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S27_MAX_BURST_SIZE = 9'd0, 
        parameter S28_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S28_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S28_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S28_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S28_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S28_MAX_BURST_SIZE = 9'd0, 
        parameter S29_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S29_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S29_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S29_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S29_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S29_MAX_BURST_SIZE = 9'd0, 
        parameter S30_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S30_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S30_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S30_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S30_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S30_MAX_BURST_SIZE = 9'd0, 
        parameter S31_FRAGMENT_EN = 1, 
        parameter [((F * 32) - 1):0] S31_BASE_ADDR = {32'h0}, 
        parameter [((F * 32) - 1):0] S31_ADDR_RANGE = {32'h400}, 
        parameter [((TOTAL_MASTER_CNT * M_PRIO_WIDTH) - 1):0] S31_M_PRIO_IDX = {4'd8,
                4'd7,
                4'd6,
                4'd5,
                4'd4,
                4'd3,
                4'd2,
                4'd1}, 
        parameter [2:0] S31_ARBITER_SCHEME = 3'b0, 
        parameter [8:0] S31_MAX_BURST_SIZE = 9'd0) (
    // -----------------------------------------------------------------------------
    // Module Parameters
    // -----------------------------------------------------------------------------
    //parameter                                     K                  = 32,
    // 05/03 prev: 0
    //--- Slave 0 -------------------------------------------------------------------
    //--- Slave 1 -------------------------------------------------------------------
    //--- Slave 2 -------------------------------------------------------------------
    //--- Slave 3 -------------------------------------------------------------------
    //--- Slave 4 -------------------------------------------------------------------
    //--- Slave 5 -------------------------------------------------------------------
    //--- Slave 6 -------------------------------------------------------------------
    //--- Slave 7 -------------------------------------------------------------------
    //--- Slave 8 -------------------------------------------------------------------
    //--- Slave 9 -------------------------------------------------------------------
    //--- Slave 10 ------------------------------------------------------------------
    //--- Slave 11 ------------------------------------------------------------------
    //--- Slave 12 ------------------------------------------------------------------
    //--- Slave 13 ------------------------------------------------------------------
    //--- Slave 14 ------------------------------------------------------------------
    //--- Slave 15 ------------------------------------------------------------------
    //--- Slave 16 ------------------------------------------------------------------
    //--- Slave 17 ------------------------------------------------------------------
    //--- Slave 18 ------------------------------------------------------------------
    //--- Slave 19 ------------------------------------------------------------------
    //--- Slave 20 ------------------------------------------------------------------
    //--- Slave 21 ------------------------------------------------------------------
    //--- Slave 22 ------------------------------------------------------------------
    //--- Slave 23 ------------------------------------------------------------------
    //--- Slave 24 ------------------------------------------------------------------
    //--- Slave 25 ------------------------------------------------------------------
    //--- Slave 26 ------------------------------------------------------------------
    //--- Slave 27 ------------------------------------------------------------------
    //--- Slave 28 ------------------------------------------------------------------
    //--- Slave 29 ------------------------------------------------------------------
    //--- Slave 30 ------------------------------------------------------------------
    //--- Slave 31 ------------------------------------------------------------------
    // ------------------------------------------------------------------------------
    // Input/Output Ports
    // ------------------------------------------------------------------------------
    input ahbl_hclk_i, 
    input ahbl_hresetn_i, 
    // -------------------------------------------
    // AHB-Lite Master Interface (to/from master)
    // -------------------------------------------
    input [(TOTAL_MASTER_CNT - 1):0] ahbl_hsel_slv_i, 
    input [((TOTAL_MASTER_CNT * M_ADDR_WIDTH) - 1):0] ahbl_haddr_slv_i, 
    input [((TOTAL_MASTER_CNT * 3) - 1):0] ahbl_hburst_slv_i, 
    input [((TOTAL_MASTER_CNT * 3) - 1):0] ahbl_hsize_slv_i, 
    input [(TOTAL_MASTER_CNT - 1):0] ahbl_hmastlock_slv_i, 
    input [((TOTAL_MASTER_CNT * 4) - 1):0] ahbl_hprot_slv_i, 
    input [((TOTAL_MASTER_CNT * 2) - 1):0] ahbl_htrans_slv_i, 
    input [((TOTAL_MASTER_CNT * DATA_WIDTH) - 1):0] ahbl_hwdata_slv_i, 
    input [(TOTAL_MASTER_CNT - 1):0] ahbl_hwrite_slv_i, 
    input [(TOTAL_MASTER_CNT - 1):0] ahbl_hready_slv_i, 
    output wire [(TOTAL_MASTER_CNT - 1):0] ahbl_hreadyout_slv_o, 
    output wire [(TOTAL_MASTER_CNT - 1):0] ahbl_hresp_slv_o, 
    output wire [((TOTAL_MASTER_CNT * DATA_WIDTH) - 1):0] ahbl_hrdata_slv_o, 
    // -----------------------------------------
    // AHB-Lite Slave Interface (to/from slave)
    // -----------------------------------------
    output wire [(TOTAL_SLAVE_CNT - 1):0] ahbl_hsel_mstr_o, 
    output wire [((TOTAL_SLAVE_CNT * M_ADDR_WIDTH) - 1):0] ahbl_haddr_mstr_o, 
    output wire [((TOTAL_SLAVE_CNT * 3) - 1):0] ahbl_hburst_mstr_o, 
    output wire [((TOTAL_SLAVE_CNT * 3) - 1):0] ahbl_hsize_mstr_o, 
    output wire [(TOTAL_SLAVE_CNT - 1):0] ahbl_hmastlock_mstr_o, 
    output wire [((TOTAL_SLAVE_CNT * 4) - 1):0] ahbl_hprot_mstr_o, 
    output wire [((TOTAL_SLAVE_CNT * 2) - 1):0] ahbl_htrans_mstr_o, 
    output wire [((TOTAL_SLAVE_CNT * DATA_WIDTH) - 1):0] ahbl_hwdata_mstr_o, 
    output wire [(TOTAL_SLAVE_CNT - 1):0] ahbl_hwrite_mstr_o, 
    output wire [(TOTAL_SLAVE_CNT - 1):0] ahbl_hready_mstr_o, 
    input [(TOTAL_SLAVE_CNT - 1):0] ahbl_hready_mstr_i, 
    input [(TOTAL_SLAVE_CNT - 1):0] ahbl_hresp_mstr_i, 
    input [((TOTAL_SLAVE_CNT * DATA_WIDTH) - 1):0] ahbl_hrdata_mstr_i) ;
    // ------------------------------------------------------------------------------
    // Local Parameters
    // ------------------------------------------------------------------------------
    // ------------------------------------------------------------------------------
    // Wire Declarations
    // ------------------------------------------------------------------------------
    // ------------------------------------------------------------------------------
    // Assign Statements
    // ------------------------------------------------------------------------------
    // ------------------------------------------------------------------------------
    // Submodule Instantiation(s)
    // ------------------------------------------------------------------------------
    generate
        if (((TOTAL_MASTER_CNT == 1) && (TOTAL_SLAVE_CNT >= 1))) 
            begin : ahb_lite_bus
                // -------------
                // AHB-Lite Bus
                // -------------
                ahbl0_ipgen_lscc_ahbl_bus #(.F(F),
                        .M_ADDR_WIDTH(M_ADDR_WIDTH),
                        .FULL_DECODE_EN(FULL_DECODE_EN),
                        .DATA_WIDTH(DATA_WIDTH),
                        .TOTAL_SLAVE_CNT(TOTAL_SLAVE_CNT),
                        .OUTREG_EN(OUTREG_EN),
                        .S0_FRAGMENT_EN(S0_FRAGMENT_EN),
                        .S0_BASE_ADDR(S0_BASE_ADDR[((F * 32) - 1):0]),
                        .S0_ADDR_RANGE(S0_ADDR_RANGE[((F * 32) - 1):0]),
                        .S1_FRAGMENT_EN(S1_FRAGMENT_EN),
                        .S1_BASE_ADDR(S1_BASE_ADDR[((F * 32) - 1):0]),
                        .S1_ADDR_RANGE(S1_ADDR_RANGE[((F * 32) - 1):0]),
                        .S2_FRAGMENT_EN(S2_FRAGMENT_EN),
                        .S2_BASE_ADDR(S2_BASE_ADDR[((F * 32) - 1):0]),
                        .S2_ADDR_RANGE(S2_ADDR_RANGE[((F * 32) - 1):0]),
                        .S3_FRAGMENT_EN(S3_FRAGMENT_EN),
                        .S3_BASE_ADDR(S3_BASE_ADDR[((F * 32) - 1):0]),
                        .S3_ADDR_RANGE(S3_ADDR_RANGE[((F * 32) - 1):0]),
                        .S4_FRAGMENT_EN(S4_FRAGMENT_EN),
                        .S4_BASE_ADDR(S4_BASE_ADDR[((F * 32) - 1):0]),
                        .S4_ADDR_RANGE(S4_ADDR_RANGE[((F * 32) - 1):0]),
                        .S5_FRAGMENT_EN(S5_FRAGMENT_EN),
                        .S5_BASE_ADDR(S5_BASE_ADDR[((F * 32) - 1):0]),
                        .S5_ADDR_RANGE(S5_ADDR_RANGE[((F * 32) - 1):0]),
                        .S6_FRAGMENT_EN(S6_FRAGMENT_EN),
                        .S6_BASE_ADDR(S6_BASE_ADDR[((F * 32) - 1):0]),
                        .S6_ADDR_RANGE(S6_ADDR_RANGE[((F * 32) - 1):0]),
                        .S7_FRAGMENT_EN(S7_FRAGMENT_EN),
                        .S7_BASE_ADDR(S7_BASE_ADDR[((F * 32) - 1):0]),
                        .S7_ADDR_RANGE(S7_ADDR_RANGE[((F * 32) - 1):0]),
                        .S8_FRAGMENT_EN(S8_FRAGMENT_EN),
                        .S8_BASE_ADDR(S8_BASE_ADDR[((F * 32) - 1):0]),
                        .S8_ADDR_RANGE(S8_ADDR_RANGE[((F * 32) - 1):0]),
                        .S9_FRAGMENT_EN(S9_FRAGMENT_EN),
                        .S9_BASE_ADDR(S9_BASE_ADDR[((F * 32) - 1):0]),
                        .S9_ADDR_RANGE(S9_ADDR_RANGE[((F * 32) - 1):0]),
                        .S10_FRAGMENT_EN(S10_FRAGMENT_EN),
                        .S10_BASE_ADDR(S10_BASE_ADDR[((F * 32) - 1):0]),
                        .S10_ADDR_RANGE(S10_ADDR_RANGE[((F * 32) - 1):0]),
                        .S11_FRAGMENT_EN(S11_FRAGMENT_EN),
                        .S11_BASE_ADDR(S11_BASE_ADDR[((F * 32) - 1):0]),
                        .S11_ADDR_RANGE(S11_ADDR_RANGE[((F * 32) - 1):0]),
                        .S12_FRAGMENT_EN(S12_FRAGMENT_EN),
                        .S12_BASE_ADDR(S12_BASE_ADDR[((F * 32) - 1):0]),
                        .S12_ADDR_RANGE(S12_ADDR_RANGE[((F * 32) - 1):0]),
                        .S13_FRAGMENT_EN(S13_FRAGMENT_EN),
                        .S13_BASE_ADDR(S13_BASE_ADDR[((F * 32) - 1):0]),
                        .S13_ADDR_RANGE(S13_ADDR_RANGE[((F * 32) - 1):0]),
                        .S14_FRAGMENT_EN(S14_FRAGMENT_EN),
                        .S14_BASE_ADDR(S14_BASE_ADDR[((F * 32) - 1):0]),
                        .S14_ADDR_RANGE(S14_ADDR_RANGE[((F * 32) - 1):0]),
                        .S15_FRAGMENT_EN(S15_FRAGMENT_EN),
                        .S15_BASE_ADDR(S15_BASE_ADDR[((F * 32) - 1):0]),
                        .S15_ADDR_RANGE(S15_ADDR_RANGE[((F * 32) - 1):0]),
                        .S16_FRAGMENT_EN(S16_FRAGMENT_EN),
                        .S16_BASE_ADDR(S16_BASE_ADDR[((F * 32) - 1):0]),
                        .S16_ADDR_RANGE(S16_ADDR_RANGE[((F * 32) - 1):0]),
                        .S17_FRAGMENT_EN(S17_FRAGMENT_EN),
                        .S17_BASE_ADDR(S17_BASE_ADDR[((F * 32) - 1):0]),
                        .S17_ADDR_RANGE(S17_ADDR_RANGE[((F * 32) - 1):0]),
                        .S18_FRAGMENT_EN(S18_FRAGMENT_EN),
                        .S18_BASE_ADDR(S18_BASE_ADDR[((F * 32) - 1):0]),
                        .S18_ADDR_RANGE(S18_ADDR_RANGE[((F * 32) - 1):0]),
                        .S19_FRAGMENT_EN(S19_FRAGMENT_EN),
                        .S19_BASE_ADDR(S19_BASE_ADDR[((F * 32) - 1):0]),
                        .S19_ADDR_RANGE(S19_ADDR_RANGE[((F * 32) - 1):0]),
                        .S20_FRAGMENT_EN(S20_FRAGMENT_EN),
                        .S20_BASE_ADDR(S20_BASE_ADDR[((F * 32) - 1):0]),
                        .S20_ADDR_RANGE(S20_ADDR_RANGE[((F * 32) - 1):0]),
                        .S21_FRAGMENT_EN(S21_FRAGMENT_EN),
                        .S21_BASE_ADDR(S21_BASE_ADDR[((F * 32) - 1):0]),
                        .S21_ADDR_RANGE(S21_ADDR_RANGE[((F * 32) - 1):0]),
                        .S22_FRAGMENT_EN(S22_FRAGMENT_EN),
                        .S22_BASE_ADDR(S22_BASE_ADDR[((F * 32) - 1):0]),
                        .S22_ADDR_RANGE(S22_ADDR_RANGE[((F * 32) - 1):0]),
                        .S23_FRAGMENT_EN(S23_FRAGMENT_EN),
                        .S23_BASE_ADDR(S23_BASE_ADDR[((F * 32) - 1):0]),
                        .S23_ADDR_RANGE(S23_ADDR_RANGE[((F * 32) - 1):0]),
                        .S24_FRAGMENT_EN(S24_FRAGMENT_EN),
                        .S24_BASE_ADDR(S24_BASE_ADDR[((F * 32) - 1):0]),
                        .S24_ADDR_RANGE(S24_ADDR_RANGE[((F * 32) - 1):0]),
                        .S25_FRAGMENT_EN(S25_FRAGMENT_EN),
                        .S25_BASE_ADDR(S25_BASE_ADDR[((F * 32) - 1):0]),
                        .S25_ADDR_RANGE(S25_ADDR_RANGE[((F * 32) - 1):0]),
                        .S26_FRAGMENT_EN(S26_FRAGMENT_EN),
                        .S26_BASE_ADDR(S26_BASE_ADDR[((F * 32) - 1):0]),
                        .S26_ADDR_RANGE(S26_ADDR_RANGE[((F * 32) - 1):0]),
                        .S27_FRAGMENT_EN(S27_FRAGMENT_EN),
                        .S27_BASE_ADDR(S27_BASE_ADDR[((F * 32) - 1):0]),
                        .S27_ADDR_RANGE(S27_ADDR_RANGE[((F * 32) - 1):0]),
                        .S28_FRAGMENT_EN(S28_FRAGMENT_EN),
                        .S28_BASE_ADDR(S28_BASE_ADDR[((F * 32) - 1):0]),
                        .S28_ADDR_RANGE(S28_ADDR_RANGE[((F * 32) - 1):0]),
                        .S29_FRAGMENT_EN(S29_FRAGMENT_EN),
                        .S29_BASE_ADDR(S29_BASE_ADDR[((F * 32) - 1):0]),
                        .S29_ADDR_RANGE(S29_ADDR_RANGE[((F * 32) - 1):0]),
                        .S30_FRAGMENT_EN(S30_FRAGMENT_EN),
                        .S30_BASE_ADDR(S30_BASE_ADDR[((F * 32) - 1):0]),
                        .S30_ADDR_RANGE(S30_ADDR_RANGE[((F * 32) - 1):0]),
                        .S31_FRAGMENT_EN(S31_FRAGMENT_EN),
                        .S31_BASE_ADDR(S31_BASE_ADDR[((F * 32) - 1):0]),
                        .S31_ADDR_RANGE(S31_ADDR_RANGE[((F * 32) - 1):0])) u_lscc_ahbl_bus (/*AUTOINSTPARAM*/ // Parameters
                        //       .K                               (K),
                        /*AUTOINST*/ // Outputs
                        .ahbl_hreadyout_slv_o(ahbl_hreadyout_slv_o), 
                            .ahbl_hresp_slv_o(ahbl_hresp_slv_o), 
                            .ahbl_hrdata_slv_o(ahbl_hrdata_slv_o[(DATA_WIDTH - 1):0]), 
                            .ahbl_hsel_mstr_o(ahbl_hsel_mstr_o), 
                            .ahbl_haddr_mstr_o(ahbl_haddr_mstr_o), 
                            .ahbl_hburst_mstr_o(ahbl_hburst_mstr_o), 
                            .ahbl_hsize_mstr_o(ahbl_hsize_mstr_o), 
                            .ahbl_hmastlock_mstr_o(ahbl_hmastlock_mstr_o), 
                            .ahbl_hprot_mstr_o(ahbl_hprot_mstr_o), 
                            .ahbl_htrans_mstr_o(ahbl_htrans_mstr_o), 
                            .ahbl_hwdata_mstr_o(ahbl_hwdata_mstr_o), 
                            .ahbl_hwrite_mstr_o(ahbl_hwrite_mstr_o), 
                            .ahbl_hready_mstr_o(ahbl_hready_mstr_o), 
                            // Inputs
                        .ahbl_hclk_i(ahbl_hclk_i), 
                            .ahbl_hresetn_i(ahbl_hresetn_i), 
                            .ahbl_hsel_slv_i(ahbl_hsel_slv_i), 
                            .ahbl_haddr_slv_i(ahbl_haddr_slv_i[(M_ADDR_WIDTH - 1):0]), 
                            .ahbl_hburst_slv_i(ahbl_hburst_slv_i[2:0]), 
                            .ahbl_hsize_slv_i(ahbl_hsize_slv_i[2:0]), 
                            .ahbl_hmastlock_slv_i(ahbl_hmastlock_slv_i), 
                            .ahbl_hprot_slv_i(ahbl_hprot_slv_i[3:0]), 
                            .ahbl_htrans_slv_i(ahbl_htrans_slv_i[1:0]), 
                            .ahbl_hwdata_slv_i(ahbl_hwdata_slv_i[(DATA_WIDTH - 1):0]), 
                            .ahbl_hwrite_slv_i(ahbl_hwrite_slv_i), 
                            .ahbl_hready_slv_i(ahbl_hready_slv_i), 
                            .ahbl_hreadyout_mstr_i(ahbl_hready_mstr_i), 
                            .ahbl_hresp_mstr_i(ahbl_hresp_mstr_i), 
                            .ahbl_hrdata_mstr_i(ahbl_hrdata_mstr_i)) ; 
            end
        //  if ((TOTAL_MASTER_CNT >= 1) && (TOTAL_SLAVE_CNT == 1)) begin : ahbl_lite_arbmux
        //    wire [TOTAL_MASTER_CNT-1:0]                ahbl_addr_stall_w;
        //    wire [TOTAL_MASTER_CNT-1:0]                ahbl_hresp_slv_w;
        //    wire [TOTAL_MASTER_CNT-1:0]                ahbl_hreadyout_slv_w;
        //    wire [TOTAL_MASTER_CNT-1:0]                ahbl_hready_slv_w;
        //    wire [(TOTAL_MASTER_CNT*2)-1:0]            ahbl_htrans_slv_w;
        //    wire [(TOTAL_MASTER_CNT*M_ADDR_WIDTH)-1:0] ahbl_haddr_slv_w;
        //    wire [(TOTAL_MASTER_CNT*3)-1:0]            ahbl_hburst_slv_w;
        //    wire [(TOTAL_MASTER_CNT*3)-1:0]            ahbl_hsize_slv_w;
        //    wire [TOTAL_MASTER_CNT-1:0]                ahbl_hmastlock_slv_w;
        //    wire [(TOTAL_MASTER_CNT*4)-1:0]            ahbl_hprot_slv_w;
        //    wire [TOTAL_MASTER_CNT-1:0]                ahbl_hwrite_slv_w;
        //    wire [TOTAL_MASTER_CNT-1:0]                ahbl_hsel_slv_w;
        //
        //    // -------------
        //    // Input Stage
        //    // -------------    
        //    genvar i;
        //    for (i = 0; i < TOTAL_MASTER_CNT; i = i + 1) begin : input_stage_reg
        //      lscc_ahbl_input_stage #
        //        (/*AUTOINSTPARAM*/
        //         // Parameters
        //         .M_ADDR_WIDTH                        (M_ADDR_WIDTH))
        //      u_lscc_ahbl_input_stage
        //        (/*AUTOINST*/
        //         // AHB-Lite Master Interface (to/from arbmux)
        //         .ahbl_hreadyout_slv_i                (ahbl_hreadyout_slv_w[i]),
        //         .ahbl_hready_slv_o                   (ahbl_hready_slv_w[i]),
        //         .ahbl_htrans_slv_o                   (ahbl_htrans_slv_w[(2*i)+:2]),
        //         .ahbl_haddr_slv_o                    (ahbl_haddr_slv_w[(M_ADDR_WIDTH*i)+:M_ADDR_WIDTH]),
        //         .ahbl_hburst_slv_o                   (ahbl_hburst_slv_w[(3*i)+:3]),
        //         .ahbl_hsize_slv_o                    (ahbl_hsize_slv_w[(3*i)+:3]),
        //         .ahbl_hmastlock_slv_o                (ahbl_hmastlock_slv_w[i]),
        //         .ahbl_hprot_slv_o                    (ahbl_hprot_slv_w[(4*i)+:4]),
        //         .ahbl_hwrite_slv_o                   (ahbl_hwrite_slv_w[i]),
        //         .ahbl_hsel_slv_o                     (ahbl_hsel_slv_w[i]),
        //         
        //         // Inputs
        //         .ahbl_hclk_i                         (ahbl_hclk_i),
        //         .ahbl_hresetn_i                      (ahbl_hresetn_i),
        //         .ahbl_addr_stall_i                   (ahbl_addr_stall_w[i]),
        //         // AHB-Lite Master Interface (to/from master)
        //         .ahbl_hreadyout_slv_o                (ahbl_hreadyout_slv_o[i]),
        //         .ahbl_hready_slv_i                   (ahbl_hready_slv_i[i]),
        //         .ahbl_htrans_slv_i                   (ahbl_htrans_slv_i[(2*i)+:2]),
        //         .ahbl_haddr_slv_i                    (ahbl_haddr_slv_i[(M_ADDR_WIDTH*i)+:M_ADDR_WIDTH]),
        //         .ahbl_hburst_slv_i                   (ahbl_hburst_slv_i[(3*i)+:3]),
        //         .ahbl_hsize_slv_i                    (ahbl_hsize_slv_i[(3*i)+:3]),
        //         .ahbl_hmastlock_slv_i                (ahbl_hmastlock_slv_i[i]),
        //         .ahbl_hprot_slv_i                    (ahbl_hprot_slv_i[(4*i)+:4]),
        //         .ahbl_hwrite_slv_i                   (ahbl_hwrite_slv_i[i]),
        //         .ahbl_hsel_slv_i                     (ahbl_hsel_slv_i[i]),
        //         .ahbl_hresp_slv_i                    (ahbl_hresp_slv_w));
        //      assign ahbl_hresp_slv_o[i] = ahbl_hresp_slv_w;
        //    end 
        //    // -----------------------------
        //    // AHB-Lite Arbiter-Multiplexor
        //    // -----------------------------
        //    lscc_ahbl_arbmux #
        //      (/*AUTOINSTPARAM*/
        //       // Parameters
        //       .K                               (K),
        //       .TOTAL_MASTER_CNT                (TOTAL_MASTER_CNT),
        //       .INPUT_STAGE                     (0), // Input stage is moved outside
        //       .M_ADDR_WIDTH                    (M_ADDR_WIDTH),
        //       .M_PRIO_IDX                      (S0_M_PRIO_IDX[TOTAL_MASTER_CNT*M_PRIO_WIDTH-1:0]),
        //       .DATA_WIDTH                      (DATA_WIDTH),
        //       .OUTREG_EN                       (OUTREG_EN),
        //       .ARBITER_SCHEME                  (S0_ARBITER_SCHEME[2:0]),
        //       .MAX_BURST_SIZE                   (S0_MAX_BURST_SIZE[TOTAL_MASTER_CNT*K-1:0]))
        //    u_lscc_ahbl_arbmux
        //      (/*AUTOINST*/
        //       .ahbl_hclk_i                     (ahbl_hclk_i),
        //       .ahbl_hresetn_i                  (ahbl_hresetn_i),
        //       .ahbl_addr_stall_o               (ahbl_addr_stall_w),
        //       // AHB-Lite Slave Interface (to/from Slave)
        //       .ahbl_hsel_mstr_o                (ahbl_hsel_mstr_o),
        //       .ahbl_haddr_mstr_o               (ahbl_haddr_mstr_o),
        //       .ahbl_hburst_mstr_o              (ahbl_hburst_mstr_o),
        //       .ahbl_hsize_mstr_o               (ahbl_hsize_mstr_o),
        //       .ahbl_hmastlock_mstr_o           (ahbl_hmastlock_mstr_o),
        //       .ahbl_hprot_mstr_o               (ahbl_hprot_mstr_o),
        //       .ahbl_htrans_mstr_o              (ahbl_htrans_mstr_o),
        //       .ahbl_hwdata_mstr_o              (ahbl_hwdata_mstr_o),
        //       .ahbl_hwrite_mstr_o              (ahbl_hwrite_mstr_o),
        //       .ahbl_hready_mstr_o              (ahbl_hready_mstr_o),
        //       .ahbl_hreadyout_mstr_i           (ahbl_hready_mstr_i),
        //       .ahbl_hresp_mstr_i               (ahbl_hresp_mstr_i),
        //       .ahbl_hrdata_mstr_i              (ahbl_hrdata_mstr_i),
        //       // AHB-Lite Master Interface (to/from Input Stage)
        //       .ahbl_hreadyout_slv_o            (ahbl_hreadyout_slv_w),
        //       .ahbl_hresp_slv_o                (ahbl_hresp_slv_w),
        //       .ahbl_hrdata_slv_o               (ahbl_hrdata_slv_o), // To port
        //       .ahbl_hsel_slv_i                 (ahbl_hsel_slv_w),
        //       .ahbl_haddr_slv_i                (ahbl_haddr_slv_w),
        //       .ahbl_hburst_slv_i               (ahbl_hburst_slv_w),
        //       .ahbl_hsize_slv_i                (ahbl_hsize_slv_w),
        //       .ahbl_hmastlock_slv_i            (ahbl_hmastlock_slv_w),
        //       .ahbl_hprot_slv_i                (ahbl_hprot_slv_w),
        //       .ahbl_htrans_slv_i               (ahbl_htrans_slv_w),
        //       .ahbl_hwdata_slv_i               (ahbl_hwdata_slv_i), // From port
        //       .ahbl_hwrite_slv_i               (ahbl_hwrite_slv_w),
        //       .ahbl_hready_slv_i               (ahbl_hready_slv_w)
        //       );
        //  end
        if (((TOTAL_MASTER_CNT > 1) && (TOTAL_SLAVE_CNT >= 1))) 
            begin : ahbl_lite_crossbar
                // ------------------
                // AHB-Lite Crossbar
                // ------------------
                ahbl0_ipgen_lscc_ahbl_crossbar #(.TOTAL_MASTER_CNT(TOTAL_MASTER_CNT),
                        .TOTAL_SLAVE_CNT(TOTAL_SLAVE_CNT),
                        .M_ADDR_WIDTH(M_ADDR_WIDTH),
                        .FULL_DECODE_EN(FULL_DECODE_EN),
                        .DATA_WIDTH(DATA_WIDTH),
                        .OUTREG_EN(OUTREG_EN),
                        .S0_FRAGMENT_EN(S0_FRAGMENT_EN),
                        .S0_BASE_ADDR(S0_BASE_ADDR),
                        .S0_ADDR_RANGE(S0_ADDR_RANGE),
                        .S0_M_PRIO_IDX(S0_M_PRIO_IDX),
                        .S0_ARBITER_SCHEME(S0_ARBITER_SCHEME),
                        .S0_MAX_BURST_SIZE(S0_MAX_BURST_SIZE),
                        .S1_FRAGMENT_EN(S1_FRAGMENT_EN),
                        .S1_BASE_ADDR(S1_BASE_ADDR),
                        .S1_ADDR_RANGE(S1_ADDR_RANGE),
                        .S1_M_PRIO_IDX(S1_M_PRIO_IDX),
                        .S1_ARBITER_SCHEME(S1_ARBITER_SCHEME),
                        .S1_MAX_BURST_SIZE(S1_MAX_BURST_SIZE),
                        .S2_FRAGMENT_EN(S2_FRAGMENT_EN),
                        .S2_BASE_ADDR(S2_BASE_ADDR),
                        .S2_ADDR_RANGE(S2_ADDR_RANGE),
                        .S2_M_PRIO_IDX(S2_M_PRIO_IDX),
                        .S2_ARBITER_SCHEME(S2_ARBITER_SCHEME),
                        .S2_MAX_BURST_SIZE(S2_MAX_BURST_SIZE),
                        .S3_FRAGMENT_EN(S3_FRAGMENT_EN),
                        .S3_BASE_ADDR(S3_BASE_ADDR),
                        .S3_ADDR_RANGE(S3_ADDR_RANGE),
                        .S3_M_PRIO_IDX(S3_M_PRIO_IDX),
                        .S3_ARBITER_SCHEME(S3_ARBITER_SCHEME),
                        .S3_MAX_BURST_SIZE(S3_MAX_BURST_SIZE),
                        .S4_FRAGMENT_EN(S4_FRAGMENT_EN),
                        .S4_BASE_ADDR(S4_BASE_ADDR),
                        .S4_ADDR_RANGE(S4_ADDR_RANGE),
                        .S4_M_PRIO_IDX(S4_M_PRIO_IDX),
                        .S4_ARBITER_SCHEME(S4_ARBITER_SCHEME),
                        .S4_MAX_BURST_SIZE(S4_MAX_BURST_SIZE),
                        .S5_FRAGMENT_EN(S5_FRAGMENT_EN),
                        .S5_BASE_ADDR(S5_BASE_ADDR),
                        .S5_ADDR_RANGE(S5_ADDR_RANGE),
                        .S5_M_PRIO_IDX(S5_M_PRIO_IDX),
                        .S5_ARBITER_SCHEME(S5_ARBITER_SCHEME),
                        .S5_MAX_BURST_SIZE(S5_MAX_BURST_SIZE),
                        .S6_FRAGMENT_EN(S6_FRAGMENT_EN),
                        .S6_BASE_ADDR(S6_BASE_ADDR),
                        .S6_ADDR_RANGE(S6_ADDR_RANGE),
                        .S6_M_PRIO_IDX(S6_M_PRIO_IDX),
                        .S6_ARBITER_SCHEME(S6_ARBITER_SCHEME),
                        .S6_MAX_BURST_SIZE(S6_MAX_BURST_SIZE),
                        .S7_FRAGMENT_EN(S7_FRAGMENT_EN),
                        .S7_BASE_ADDR(S7_BASE_ADDR),
                        .S7_ADDR_RANGE(S7_ADDR_RANGE),
                        .S7_M_PRIO_IDX(S7_M_PRIO_IDX),
                        .S7_ARBITER_SCHEME(S7_ARBITER_SCHEME),
                        .S7_MAX_BURST_SIZE(S7_MAX_BURST_SIZE),
                        .S8_FRAGMENT_EN(S8_FRAGMENT_EN),
                        .S8_BASE_ADDR(S8_BASE_ADDR),
                        .S8_ADDR_RANGE(S8_ADDR_RANGE),
                        .S8_M_PRIO_IDX(S8_M_PRIO_IDX),
                        .S8_ARBITER_SCHEME(S8_ARBITER_SCHEME),
                        .S8_MAX_BURST_SIZE(S8_MAX_BURST_SIZE),
                        .S9_FRAGMENT_EN(S9_FRAGMENT_EN),
                        .S9_BASE_ADDR(S9_BASE_ADDR),
                        .S9_ADDR_RANGE(S9_ADDR_RANGE),
                        .S9_M_PRIO_IDX(S9_M_PRIO_IDX),
                        .S9_ARBITER_SCHEME(S9_ARBITER_SCHEME),
                        .S9_MAX_BURST_SIZE(S9_MAX_BURST_SIZE),
                        .S10_FRAGMENT_EN(S10_FRAGMENT_EN),
                        .S10_BASE_ADDR(S10_BASE_ADDR),
                        .S10_ADDR_RANGE(S10_ADDR_RANGE),
                        .S10_M_PRIO_IDX(S10_M_PRIO_IDX),
                        .S10_ARBITER_SCHEME(S10_ARBITER_SCHEME),
                        .S10_MAX_BURST_SIZE(S10_MAX_BURST_SIZE),
                        .S11_FRAGMENT_EN(S11_FRAGMENT_EN),
                        .S11_BASE_ADDR(S11_BASE_ADDR),
                        .S11_ADDR_RANGE(S11_ADDR_RANGE),
                        .S11_M_PRIO_IDX(S11_M_PRIO_IDX),
                        .S11_ARBITER_SCHEME(S11_ARBITER_SCHEME),
                        .S11_MAX_BURST_SIZE(S11_MAX_BURST_SIZE),
                        .S12_FRAGMENT_EN(S12_FRAGMENT_EN),
                        .S12_BASE_ADDR(S12_BASE_ADDR),
                        .S12_ADDR_RANGE(S12_ADDR_RANGE),
                        .S12_M_PRIO_IDX(S12_M_PRIO_IDX),
                        .S12_ARBITER_SCHEME(S12_ARBITER_SCHEME),
                        .S12_MAX_BURST_SIZE(S12_MAX_BURST_SIZE),
                        .S13_FRAGMENT_EN(S13_FRAGMENT_EN),
                        .S13_BASE_ADDR(S13_BASE_ADDR),
                        .S13_ADDR_RANGE(S13_ADDR_RANGE),
                        .S13_M_PRIO_IDX(S13_M_PRIO_IDX),
                        .S13_ARBITER_SCHEME(S13_ARBITER_SCHEME),
                        .S13_MAX_BURST_SIZE(S13_MAX_BURST_SIZE),
                        .S14_FRAGMENT_EN(S14_FRAGMENT_EN),
                        .S14_BASE_ADDR(S14_BASE_ADDR),
                        .S14_ADDR_RANGE(S14_ADDR_RANGE),
                        .S14_M_PRIO_IDX(S14_M_PRIO_IDX),
                        .S14_ARBITER_SCHEME(S14_ARBITER_SCHEME),
                        .S14_MAX_BURST_SIZE(S14_MAX_BURST_SIZE),
                        .S15_FRAGMENT_EN(S15_FRAGMENT_EN),
                        .S15_BASE_ADDR(S15_BASE_ADDR),
                        .S15_ADDR_RANGE(S15_ADDR_RANGE),
                        .S15_M_PRIO_IDX(S15_M_PRIO_IDX),
                        .S15_ARBITER_SCHEME(S15_ARBITER_SCHEME),
                        .S15_MAX_BURST_SIZE(S15_MAX_BURST_SIZE),
                        .S16_FRAGMENT_EN(S16_FRAGMENT_EN),
                        .S16_BASE_ADDR(S16_BASE_ADDR),
                        .S16_ADDR_RANGE(S16_ADDR_RANGE),
                        .S16_M_PRIO_IDX(S16_M_PRIO_IDX),
                        .S16_ARBITER_SCHEME(S16_ARBITER_SCHEME),
                        .S16_MAX_BURST_SIZE(S16_MAX_BURST_SIZE),
                        .S17_FRAGMENT_EN(S17_FRAGMENT_EN),
                        .S17_BASE_ADDR(S17_BASE_ADDR),
                        .S17_ADDR_RANGE(S17_ADDR_RANGE),
                        .S17_M_PRIO_IDX(S17_M_PRIO_IDX),
                        .S17_ARBITER_SCHEME(S17_ARBITER_SCHEME),
                        .S17_MAX_BURST_SIZE(S17_MAX_BURST_SIZE),
                        .S18_FRAGMENT_EN(S18_FRAGMENT_EN),
                        .S18_BASE_ADDR(S18_BASE_ADDR),
                        .S18_ADDR_RANGE(S18_ADDR_RANGE),
                        .S18_M_PRIO_IDX(S18_M_PRIO_IDX),
                        .S18_ARBITER_SCHEME(S18_ARBITER_SCHEME),
                        .S18_MAX_BURST_SIZE(S18_MAX_BURST_SIZE),
                        .S19_FRAGMENT_EN(S19_FRAGMENT_EN),
                        .S19_BASE_ADDR(S19_BASE_ADDR),
                        .S19_ADDR_RANGE(S19_ADDR_RANGE),
                        .S19_M_PRIO_IDX(S19_M_PRIO_IDX),
                        .S19_ARBITER_SCHEME(S19_ARBITER_SCHEME),
                        .S19_MAX_BURST_SIZE(S19_MAX_BURST_SIZE),
                        .S20_FRAGMENT_EN(S20_FRAGMENT_EN),
                        .S20_BASE_ADDR(S20_BASE_ADDR),
                        .S20_ADDR_RANGE(S20_ADDR_RANGE),
                        .S20_M_PRIO_IDX(S20_M_PRIO_IDX),
                        .S20_ARBITER_SCHEME(S20_ARBITER_SCHEME),
                        .S20_MAX_BURST_SIZE(S20_MAX_BURST_SIZE),
                        .S21_FRAGMENT_EN(S21_FRAGMENT_EN),
                        .S21_BASE_ADDR(S21_BASE_ADDR),
                        .S21_ADDR_RANGE(S21_ADDR_RANGE),
                        .S21_M_PRIO_IDX(S21_M_PRIO_IDX),
                        .S21_ARBITER_SCHEME(S21_ARBITER_SCHEME),
                        .S21_MAX_BURST_SIZE(S21_MAX_BURST_SIZE),
                        .S22_FRAGMENT_EN(S22_FRAGMENT_EN),
                        .S22_BASE_ADDR(S22_BASE_ADDR),
                        .S22_ADDR_RANGE(S22_ADDR_RANGE),
                        .S22_M_PRIO_IDX(S22_M_PRIO_IDX),
                        .S22_ARBITER_SCHEME(S22_ARBITER_SCHEME),
                        .S22_MAX_BURST_SIZE(S22_MAX_BURST_SIZE),
                        .S23_FRAGMENT_EN(S23_FRAGMENT_EN),
                        .S23_BASE_ADDR(S23_BASE_ADDR),
                        .S23_ADDR_RANGE(S23_ADDR_RANGE),
                        .S23_M_PRIO_IDX(S23_M_PRIO_IDX),
                        .S23_ARBITER_SCHEME(S23_ARBITER_SCHEME),
                        .S23_MAX_BURST_SIZE(S23_MAX_BURST_SIZE),
                        .S24_FRAGMENT_EN(S24_FRAGMENT_EN),
                        .S24_BASE_ADDR(S24_BASE_ADDR),
                        .S24_ADDR_RANGE(S24_ADDR_RANGE),
                        .S24_M_PRIO_IDX(S24_M_PRIO_IDX),
                        .S24_ARBITER_SCHEME(S24_ARBITER_SCHEME),
                        .S24_MAX_BURST_SIZE(S24_MAX_BURST_SIZE),
                        .S25_FRAGMENT_EN(S25_FRAGMENT_EN),
                        .S25_BASE_ADDR(S25_BASE_ADDR),
                        .S25_ADDR_RANGE(S25_ADDR_RANGE),
                        .S25_M_PRIO_IDX(S25_M_PRIO_IDX),
                        .S25_ARBITER_SCHEME(S25_ARBITER_SCHEME),
                        .S25_MAX_BURST_SIZE(S25_MAX_BURST_SIZE),
                        .S26_FRAGMENT_EN(S26_FRAGMENT_EN),
                        .S26_BASE_ADDR(S26_BASE_ADDR),
                        .S26_ADDR_RANGE(S26_ADDR_RANGE),
                        .S26_M_PRIO_IDX(S26_M_PRIO_IDX),
                        .S26_ARBITER_SCHEME(S26_ARBITER_SCHEME),
                        .S26_MAX_BURST_SIZE(S26_MAX_BURST_SIZE),
                        .S27_FRAGMENT_EN(S27_FRAGMENT_EN),
                        .S27_BASE_ADDR(S27_BASE_ADDR),
                        .S27_ADDR_RANGE(S27_ADDR_RANGE),
                        .S27_M_PRIO_IDX(S27_M_PRIO_IDX),
                        .S27_ARBITER_SCHEME(S27_ARBITER_SCHEME),
                        .S27_MAX_BURST_SIZE(S27_MAX_BURST_SIZE),
                        .S28_FRAGMENT_EN(S28_FRAGMENT_EN),
                        .S28_BASE_ADDR(S28_BASE_ADDR),
                        .S28_ADDR_RANGE(S28_ADDR_RANGE),
                        .S28_M_PRIO_IDX(S28_M_PRIO_IDX),
                        .S28_ARBITER_SCHEME(S28_ARBITER_SCHEME),
                        .S28_MAX_BURST_SIZE(S28_MAX_BURST_SIZE),
                        .S29_FRAGMENT_EN(S29_FRAGMENT_EN),
                        .S29_BASE_ADDR(S29_BASE_ADDR),
                        .S29_ADDR_RANGE(S29_ADDR_RANGE),
                        .S29_M_PRIO_IDX(S29_M_PRIO_IDX),
                        .S29_ARBITER_SCHEME(S29_ARBITER_SCHEME),
                        .S29_MAX_BURST_SIZE(S29_MAX_BURST_SIZE),
                        .S30_FRAGMENT_EN(S30_FRAGMENT_EN),
                        .S30_BASE_ADDR(S30_BASE_ADDR),
                        .S30_ADDR_RANGE(S30_ADDR_RANGE),
                        .S30_M_PRIO_IDX(S30_M_PRIO_IDX),
                        .S30_ARBITER_SCHEME(S30_ARBITER_SCHEME),
                        .S30_MAX_BURST_SIZE(S30_MAX_BURST_SIZE),
                        .S31_FRAGMENT_EN(S31_FRAGMENT_EN),
                        .S31_BASE_ADDR(S31_BASE_ADDR),
                        .S31_ADDR_RANGE(S31_ADDR_RANGE),
                        .S31_M_PRIO_IDX(S31_M_PRIO_IDX),
                        .S31_ARBITER_SCHEME(S31_ARBITER_SCHEME),
                        .S31_MAX_BURST_SIZE(S31_MAX_BURST_SIZE)) u_lscc_ahbl_crossbar (/*AUTOINSTPARAM*/ // Parameters
                        //       .K                               (K),
                        /*AUTOINST*/ // Outputs
                        .ahbl_hreadyout_slv_o(ahbl_hreadyout_slv_o), 
                            .ahbl_hresp_slv_o(ahbl_hresp_slv_o), 
                            .ahbl_hrdata_slv_o(ahbl_hrdata_slv_o), 
                            .ahbl_hsel_mstr_o(ahbl_hsel_mstr_o), 
                            .ahbl_haddr_mstr_o(ahbl_haddr_mstr_o), 
                            .ahbl_hburst_mstr_o(ahbl_hburst_mstr_o), 
                            .ahbl_hsize_mstr_o(ahbl_hsize_mstr_o), 
                            .ahbl_hmastlock_mstr_o(ahbl_hmastlock_mstr_o), 
                            .ahbl_hprot_mstr_o(ahbl_hprot_mstr_o), 
                            .ahbl_htrans_mstr_o(ahbl_htrans_mstr_o), 
                            .ahbl_hwdata_mstr_o(ahbl_hwdata_mstr_o), 
                            .ahbl_hwrite_mstr_o(ahbl_hwrite_mstr_o), 
                            .ahbl_hready_mstr_o(ahbl_hready_mstr_o), 
                            // Inputs
                        .ahbl_hclk_i(ahbl_hclk_i), 
                            .ahbl_hresetn_i(ahbl_hresetn_i), 
                            .ahbl_hsel_slv_i(ahbl_hsel_slv_i), 
                            .ahbl_haddr_slv_i(ahbl_haddr_slv_i), 
                            .ahbl_hburst_slv_i(ahbl_hburst_slv_i), 
                            .ahbl_hsize_slv_i(ahbl_hsize_slv_i), 
                            .ahbl_hmastlock_slv_i(ahbl_hmastlock_slv_i), 
                            .ahbl_hprot_slv_i(ahbl_hprot_slv_i), 
                            .ahbl_htrans_slv_i(ahbl_htrans_slv_i), 
                            .ahbl_hwdata_slv_i(ahbl_hwdata_slv_i), 
                            .ahbl_hwrite_slv_i(ahbl_hwrite_slv_i), 
                            .ahbl_hready_slv_i(ahbl_hready_slv_i), 
                            .ahbl_hreadyout_mstr_i(ahbl_hready_mstr_i), 
                            .ahbl_hresp_mstr_i(ahbl_hresp_mstr_i), 
                            .ahbl_hrdata_mstr_i(ahbl_hrdata_mstr_i)) ; 
            end
    endgenerate
    // ------------------------------------------------------------------------------
    // Function Definition
    // ------------------------------------------------------------------------------
    function integer clog2( 
        input integer depth )  ; 
        begin
            if ((depth == 0)) 
                clog2 = 1 ;
            else
                for (clog2 = 0 ; (depth > 0) ; clog2 = (clog2 + 1))
                    depth = (depth >> 1) ;
        end
    endfunction
endmodule


