                             Lattice Mapping Report File

    Design:  eval_top
    Family:  LFCPNX
    Device:  LFCPNX-100
    Package: BBG484
    Performance Grade:  9_High-Performance_1.0V

    Mapper:    version Radiant Software (64-bit) 2023.2.0.38.1  Patch Version(s)
         20248
    Mapped on: Mon Mar 18 12:34:09 2024

    Design Information

    Command line:   map -i lpddr4_axi_201_impl_1_syn.udb -pdc /media/d480/GitHubProj
         ects/TssTechnique/TssProjects/TssSemaDuinoQualif/td201_221014/lpddr4_axi/lp
         ddr4_axi_201/constraint_201.pdc -o lpddr4_axi_201_impl_1_map.udb -mp
         lpddr4_axi_201_impl_1.mrp -hierrpt -gui -msgset /media/d480/GitHubProjects/
         TssTechnique/TssProjects/TssSemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_
         axi_201/promote.xml

    Design Summary

       Number of registers:        10708 out of 80769 (13%)
          Number of SLICE         registers: 10708 out of 79872 (13%)
          Number of PIO Input     registers:    0 out of   299 (0%)
          Number of PIO Output    registers:    0 out of   299 (0%)
          Number of PIO Tri-State registers:    0 out of   299 (0%)
       Number of LUT4s:            18915 out of 79872 (24%)
          Number used as logic LUT4s:                       15479
          Number used as distributed RAM:                   1080 (6 per 16X4 RAM)
          Number used as ripple logic:                      2356 (2 per CCU2)
       Number of PIOs used/reserved:   69 out of   299 (23%)
          Number of PIOs reserved:      7 (per sysConfig and/or prohibit constraint)
          Number of PIOs used:         62
            Number of PIOs used for single ended IO:        54
            Number of PIO pairs used for differential IO:    4
            Number allocated to regular speed PIOs:    27 out of  167 (16%)
            Number allocated to high speed PIOs:       35 out of  132 (27%)
       Number of Dedicated IO used for ADC/PCS/PCIE:    0 out of   60 (0%)
       Number of IDDR/ODDR/TDDR functions used:     65 out of   730 (9%)
          Number of IDDR functions:               16
                    IDDRX4:          16
          Number of ODDR functions:               29
                    ODDRX4:          29
          Number of TDDR functions:               20
                    TDDRX4:          20
       Number of IOs using at least one DDR function: 29 (3 differential)
          Number of IOs using IDDR only:           0 (0 differential)
          Number of IOs using ODDR only:           9 (1 differential)
          Number of IOs using ODDR/TDDR:           4 (2 differential)
          Number of IOs using IDDR/ODDR/TDDR:     16 (0 differential)
       Number of Block RAMs:          41 out of 208 (20%)
       Number of Large RAMs:          0 out of 7 (0%)
       Number of Logical DSP Functions:
          Number of Pre-Adders (9+9):    0 out of 312 (0%)
          Number of Multipliers (18x18): 0 out of 156 (0%)
             Number of 9X9:        0 (1 18x18 = 2   9x9)
             Number of 18x18:      0 (1 18x18 = 1 18x18)
             Number of 18x36:      0 (2 18x18 = 1 18x36)
             Number of 36x36:      0 (4 18x18 = 1 36x36)
          Number of 54-bit Accumulators: 0 out of 78 (0%)
          Number of 18-bit Registers:    0 out of 312 (0%)
       Number of Physical DSP Components:
          Number of PREADD9:             0 out of 312 (0%)
          Number of MULT9:               0 out of 312 (0%)
          Number of MULT18:              0 out of 156 (0%)
          Number of MULT18X36:           0 out of 78 (0%)
          Number of MULT36:              0 out of 39 (0%)
          Number of ACC54:               0 out of 78 (0%)
          Number of REG18:               0 out of 312 (0%)
       Number of ALUREGs:             0 out of 1 (0%)
       Number of PLLs:                2 out of 4 (50%)
       Number of DDRDLLs:             1 out of 2 (50%)
       Number of DLLDELs:             0 out of 10 (0%)
       Number of DQSs:                2 out of 11 (18%)
       Number of DCSs:                0 out of 2 (0%)
       Number of DCCs:                0 out of 62 (0%)
       Number of PCLKDIVs:            0 out of 2 (0%)
       Number of ECLKDIVs:            1 out of 12 (8%)
       Number of ECLKSYNCs:           1 out of 12 (8%)
       Number of ADC Blocks:          0 out of 1 (0%)
       Number of SGMIICDRs:           0 out of 2 (0%)
       Number of PMUs:                0 out of 1 (0%)
       Number of BNKREF18s:           0 out of 3 (0%)
       Number of BNKREF33s:           0 out of 5 (0%)
       Number of I2CFIFOs:            0 out of 1 (0%)
       Number of Oscillators:         1 out of 1 (100%)
       Number of GSR:                 0 out of 1 (0%)
       Number of Cryptographic Block: 0 out of 1 (0%)
       Number of Config IP:           0 out of 1 (0%)
                     TSALL:           0 out of 1 (0%)
       Number of JTAG:                0 out of 1 (0%)
       Number of SED:                 0 out of 1 (0%)
       Number of PCSs:                0 out of 2 (0%)
       Number of PCIE Link Layers:    0 out of 1 (0%)
       Number of Clocks:  13
          Net out_clk1_c: 2770 loads, 2770 rising, 0 falling (Driver: Pin ASYNC_AXI.
         u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS)
          Net clk_w: 1921 loads, 1921 rising, 0 falling (Driver: Pin ASYNC_AXI.u_acl
         k_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP)
          Net sclk_o: 6014 loads, 6014 rising, 0 falling (Driver: Pin u_mem.lscc_lpd
         dr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst/DIVOUT)
          Net osc_clk_90: 1 loads, 1 rising, 0 falling (Driver: Pin
         osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst/HFCLKOUT)
          Net pll_refclk_i_c: 1 loads, 1 rising, 0 falling (Driver: Port
         pll_refclk_i)
          Net u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w: 1 loads, 1 rising, 0
         falling (Driver: Pin u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk
         _mon.u_PLL.PLL_inst/CLKOS)
          Net u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w: 33 loads, 33 rising, 0
         falling (Driver: Pin u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_EC
         LKSYNC.ECLKSYNC_inst/ECLKOUT)
          Net u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw_w[0]: 1 loads, 1
         rising, 0 falling (Driver: Pin u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_
         dm.DQSBUF[0].VREF.u0_DQSBUF.DQSBUFA_inst/DQSW)
          Net u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw270_w[1]: 9 loads,
         9 rising, 0 falling (Driver: Pin u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dq
         s_dm.DQSBUF[1].VREF.u0_DQSBUF.DQSBUFA_inst/DQSW270)
          Net u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw_w[1]: 1 loads, 1
         rising, 0 falling (Driver: Pin u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_
         dm.DQSBUF[1].VREF.u0_DQSBUF.DQSBUFA_inst/DQSW)
          Net u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw270_w[0]: 9 loads,
         9 rising, 0 falling (Driver: Pin u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dq
         s_dm.DQSBUF[0].VREF.u0_DQSBUF.DQSBUFA_inst/DQSW270)
          Net u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsr90_w[0]: 8 loads, 8
         rising, 0 falling (Driver: Pin u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_
         dm.DQSBUF[0].VREF.u0_DQSBUF.DQSBUFA_inst/DQSR90)
          Net u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsr90_w[1]: 8 loads, 8
         rising, 0 falling (Driver: Pin u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_
         dm.DQSBUF[1].VREF.u0_DQSBUF.DQSBUFA_inst/DQSR90)
       Number of Clock Enables:  344
          Net axi_wstrb_i[0]: 18 loads, 0 SLICEs
          Net u_tragen.cpu0_M1_DATA_HREADYOUT_interconnect: 33 loads, 33 SLICEs
          Net u_tragen.out_clk1_c_enable_1517: 5 loads, 5 SLICEs
          Net u_tragen.out_clk1_c_enable_1126: 48 loads, 48 SLICEs
          Net u_tragen.ahbl_req_rdy_w: 14 loads, 14 SLICEs
          Net u_tragen.uart0_inst.lscc_uart_inst.u_rxcver.out_clk1_c_enable_980: 8
         loads, 8 SLICEs
          Net u_tragen.uart0_inst.lscc_uart_inst.u_rxcver.out_clk1_c_enable_64: 1
         loads, 1 SLICEs
          Net u_tragen.uart0_inst.lscc_uart_inst.u_rxcver.out_clk1_c_enable_65: 1
         loads, 1 SLICEs
          Net u_tragen.out_clk1_c_enable_943: 8 loads, 8 SLICEs
          Net u_tragen.out_clk1_c_enable_950: 8 loads, 8 SLICEs
          Net u_tragen.out_clk1_c_enable_952: 3 loads, 3 SLICEs
          Net u_tragen.out_clk1_c_enable_958: 7 loads, 7 SLICEs
          Net u_tragen.out_clk1_c_enable_965: 8 loads, 8 SLICEs
          Net u_tragen.out_clk1_c_enable_973: 8 loads, 8 SLICEs
          Net out_clk1_c_enable_238: 32 loads, 32 SLICEs
          Net u_tragen.out_clk1_c_enable_1027: 44 loads, 44 SLICEs
          Net u_tragen.gpio0_inst.lscc_gpio_inst.genblk2.lscc_apb2lmmi_0.out_clk1_c_
         enable_1151: 10 loads, 10 SLICEs
          Net ahbl2apb0_inst_APB_M0_interconnect_PSELx_interconnect: 4 loads, 4
         SLICEs
          Net
         u_tragen.gpio0_inst.lscc_gpio_inst.genblk2.lscc_apb2lmmi_0.bus_sm_ns[1]: 14
         loads, 14 SLICEs
          Net u_tragen.gpio0_inst.lscc_gpio_inst.genblk2.lscc_apb2lmmi_0.out_clk1_c_
         enable_48: 1 loads, 1 SLICEs
          Net u_tragen.gpio0_inst.lscc_gpio_inst.LxxNX.lscc_gpio_lmmi_0.out_clk1_c_e
         nable_1269: 10 loads, 10 SLICEs
          Net u_tragen.gpio0_inst.lscc_gpio_inst.LxxNX.lscc_gpio_lmmi_0.out_clk1_c_e
         nable_936: 10 loads, 10 SLICEs
          Net u_tragen.gpio0_inst.lscc_gpio_inst.LxxNX.lscc_gpio_lmmi_0.out_clk1_c_e
         nable_154: 10 loads, 10 SLICEs
          Net u_tragen.out_clk1_c_enable_927: 10 loads, 10 SLICEs
          Net u_tragen.out_clk1_c_enable_1390: 10 loads, 10 SLICEs
          Net u_tragen.cpu0_inst.out_clk1_c_enable_1043: 9 loads, 9 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.out_clk1_c_enable_411: 3 loads, 3 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.out_clk1_c_enable_1534: 2 loads, 2 SLICEs
          Net u_tragen.cpu0_inst.i_cpu._zz_142_: 32 loads, 32 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.out_clk1_c_enable_502: 5 loads, 5 SLICEs
          Net u_tragen.cpu0_inst_AHBL_M0_INSTR_interconnect_HREADYOUT_interconnect:
         1 loads, 1 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.out_clk1_c_enable_591: 30 loads, 30 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.out_clk1_c_enable_1208: 1 loads, 1 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.out_clk1_c_enable_695: 2 loads, 2 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.out_clk1_c_enable_790: 50 loads, 50 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.out_clk1_c_enable_498: 2 loads, 2 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.out_clk1_c_enable_639: 30 loads, 30 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.out_clk1_c_enable_1100: 50 loads, 50 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.out_clk1_c_enable_1092: 50 loads, 50 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.out_clk1_c_enable_1101: 50 loads, 50 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.out_clk1_c_enable_1075: 49 loads, 49 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.out_clk1
         _c_enable_1152: 1 loads, 1 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_perf_calc.clk_w_enable_723: 32 loads,
         32 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_perf_calc.clk_w_enable_724: 32 loads,
         32 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_perf_calc.a_duration_cntr_en_r: 17
         loads, 17 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_perf_calc.a2s_duration_cntr_en_r2: 32
         loads, 32 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_wr.mux_awsize_r[2]: 3 loads, 3 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_wr.clk_w_enable_390: 1 loads, 1
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_wr.clk_w_enable_29: 1 loads, 1 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_wr.clk_w_enable_397: 8 loads, 8
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_wr.clk_w_enable_684: 21 loads, 21
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_wr.clk_w_enable_858: 32 loads, 32
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_wr.clk_w_enable_864: 21 loads, 21
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_wr.clk_w_enable_857: 128 loads, 128
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_wr.clk_w_enable_28: 1 loads, 1 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_wr.clk_w_enable_212: 6 loads, 6
         SLICEs
          Net areset_n_i: 2 loads, 2 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_wr.u_a2d_fifo.lscc_fifo_inst.fifo0._F
         ABRIC.u_fifo.clk_w_enable_735: 4 loads, 4 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_wr.u_a2d_fifo.lscc_fifo_inst.fifo0._F
         ABRIC.u_fifo.clk_w_enable_732: 4 loads, 4 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_wr.u_a2d_fifo.lscc_fifo_inst.fifo0._F
         ABRIC.u_fifo.rd_fifo_en_w: 5 loads, 5 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_wr.a2d_wr_en_nxt_N_13675[0]: 10
         loads, 10 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_wr.clk_w_enable_70: 1 loads, 1 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_wr.clk_w_enable_71: 1 loads, 1 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_wr.clk_w_enable_72: 1 loads, 1 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_wr.clk_w_enable_74: 1 loads, 1 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_rd.mux_arsize_r[2]: 3 loads, 3 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_rd.clk_w_enable_829: 1 loads, 1
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_rd.clk_w_enable_776: 21 loads, 21
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_rd.clk_w_enable_753: 6 loads, 6
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_rd.clk_w_enable_831: 1 loads, 1
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_rd.clk_w_enable_73: 1 loads, 1 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_rd.clk_w_enable_755: 128 loads, 128
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_rd.clk_w_enable_722: 32 loads, 32
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_rd.clk_w_enable_683: 21 loads, 21
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_rd.clk_w_enable_58: 8 loads, 8 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_rd.u_a2d_fifo.lscc_fifo_inst.fifo0._F
         ABRIC.u_fifo.rd_fifo_en_w: 5 loads, 5 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_rd.u_a2d_fifo.lscc_fifo_inst.fifo0._F
         ABRIC.u_fifo.clk_w_enable_544: 4 loads, 4 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_rd.u_a2d_fifo.lscc_fifo_inst.fifo0._F
         ABRIC.u_fifo.clk_w_enable_541: 4 loads, 4 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_rd.clk_w_enable_757: 10 loads, 10
         SLICEs
          Net u_tragen.axi_tragen_inst.a_rd_error_occur_o: 2 loads, 2 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_rd.clk_w_enable_650: 1 loads, 1
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_rd.clk_w_enable_651: 1 loads, 1
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_rd.clk_w_enable_652: 1 loads, 1
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_rd.clk_w_enable_653: 1 loads, 1
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_rd.clk_w_enable_654: 1 loads, 1
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_csr.clk_w_enable_798: 5 loads, 5
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_csr.clk_w_enable_775: 20 loads, 20
         SLICEs
          Net u_tragen.apb_rd_r: 32 loads, 32 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_csr.out_clk1_c_enable_413: 2 loads, 2
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_csr.out_clk1_c_enable_416: 2 loads, 2
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_csr.out_clk1_c_enable_918: 14 loads,
         14 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_csr.out_clk1_c_enable_644: 6 loads, 6
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_csr.out_clk1_c_enable_802: 6 loads, 6
         SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_csr.out_clk1_c_enable_821: 20 loads,
         20 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_csr.out_clk1_c_enable_1527: 96 loads,
         96 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_csr.out_clk1_c_enable_726: 32 loads,
         32 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_csr.out_clk1_c_enable_694: 32 loads,
         32 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_csr.out_clk1_c_enable_418: 29 loads,
         29 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_csr.out_clk1_c_enable_852: 32 loads,
         32 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_csr.out_clk1_c_enable_797: 15 loads,
         15 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_csr.out_clk1_c_enable_663: 20 loads,
         20 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_csr.out_clk1_c_enable_914: 32 loads,
         32 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_csr.out_clk1_c_enable_760: 32 loads,
         32 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_csr.out_clk1_c_enable_883: 32 loads,
         32 SLICEs
          Net u_tragen.out_clk1_c_enable_52: 1 loads, 1 SLICEs
          Net u_tragen.out_clk1_c_enable_50: 1 loads, 1 SLICEs
          Net u_tragen.ahbl2apb0_inst.lscc_ahbl2apb_inst.out_clk1_c_enable_1523: 32
         loads, 32 SLICEs
          Net u_tragen.ahbl2apb0_inst.lscc_ahbl2apb_inst.out_clk1_c_enable_1: 1
         loads, 1 SLICEs
          Net u_tragen.ahbl0_inst.lscc_ahbl_interconnect_inst.ahb_lite_bus.u_lscc_ah
         bl_bus.u_lscc_ahbl_multiplexor.out_clk1_c_enable_385: 1 loads, 1 SLICEs
          Net u_tragen.ahbl0_inst.lscc_ahbl_interconnect_inst.ahb_lite_bus.u_lscc_ah
         bl_bus.u_lscc_ahbl_multiplexor.out_clk1_c_enable_1028: 3 loads, 3 SLICEs
          Net u_tragen.IMPL.sysmem0_inst.lscc_sys_mem_inst.mem0_req_arb_w: 16 loads,
         0 SLICEs
          Net u_tragen.IMPL.sysmem0_inst.lscc_sys_mem_inst.mem1_req_arb_w: 16 loads,
         0 SLICEs
          Net u_tragen.IMPL.sysmem0_inst.lscc_sys_mem_inst.bridge_s0.bridge_s0.out_c
         lk1_c_enable_51: 1 loads, 1 SLICEs
          Net sclk_o_enable_1022: 22 loads, 22 SLICEs
          Net kitcar_inst.enable: 3 loads, 3 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u1_mem_sync.out_clk1_
         c_enable_985: 6 loads, 6 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u1_mem_sync.out_clk1_
         c_enable_986: 2 loads, 2 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.phy_srst_n: 1 loads, 1 SLICEs
          Net
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.CA_GRP_ENA.u_ca_grp.sclk_o_enable_1242:
         3 loads, 3 SLICEs
          Net
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.CA_GRP_ENA.u_ca_grp.sclk_o_enable_1701:
         5 loads, 5 SLICEs
          Net
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.CA_GRP_ENA.u_ca_grp.sclk_o_enable_1243:
         1 loads, 1 SLICEs
          Net secured_signal_9468: 16 loads, 16 SLICEs
          Net secured_signal_9826: 3 loads, 3 SLICEs
          Net secured_signal_9901: 4 loads, 4 SLICEs
          Net secured_signal_9902: 3 loads, 3 SLICEs
          Net secured_signal_9937: 17 loads, 17 SLICEs
          Net secured_signal_10879: 28 loads, 28 SLICEs
          Net secured_signal_10880: 28 loads, 28 SLICEs
          Net secured_signal_10997: 10 loads, 10 SLICEs
          Net secured_signal_11014: 32 loads, 32 SLICEs
          Net secured_signal_11016: 2 loads, 2 SLICEs
          Net secured_signal_11017: 32 loads, 32 SLICEs
          Net secured_signal_11020: 10 loads, 10 SLICEs
          Net secured_signal_11022: 5 loads, 5 SLICEs
          Net secured_signal_11034: 10 loads, 10 SLICEs
          Net secured_signal_11035: 1 loads, 1 SLICEs
          Net secured_signal_11334: 25 loads, 25 SLICEs
          Net secured_signal_11339: 7 loads, 7 SLICEs
          Net secured_signal_11340: 18 loads, 18 SLICEs
          Net secured_signal_11342: 5 loads, 5 SLICEs
          Net secured_signal_11343: 2 loads, 2 SLICEs
          Net secured_signal_11344: 9 loads, 9 SLICEs
          Net secured_signal_11345: 4 loads, 4 SLICEs
          Net secured_signal_11346: 7 loads, 7 SLICEs
          Net secured_signal_11373: 16 loads, 16 SLICEs
          Net secured_signal_11374: 16 loads, 16 SLICEs
          Net secured_signal_11462: 8 loads, 8 SLICEs
          Net secured_signal_11599: 4 loads, 4 SLICEs
          Net secured_signal_11601: 4 loads, 4 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.out_clk1_c_enable_145: 44 loads, 44 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.out_clk1_c_enable_325: 44 loads, 44 SLICEs
          Net secured_signal_12127: 33 loads, 33 SLICEs
          Net secured_signal_12236: 4 loads, 4 SLICEs
          Net secured_signal_12239: 1 loads, 1 SLICEs
          Net secured_signal_12258: 1 loads, 1 SLICEs
          Net secured_signal_12261: 1 loads, 1 SLICEs
          Net secured_signal_12313: 12 loads, 12 SLICEs
          Net secured_signal_12670: 1 loads, 1 SLICEs
          Net secured_signal_12676: 50 loads, 50 SLICEs
          Net secured_signal_12684: 31 loads, 31 SLICEs
          Net secured_signal_12744: 2 loads, 2 SLICEs
          Net secured_signal_13424: 3 loads, 3 SLICEs
          Net secured_signal_13485: 5 loads, 5 SLICEs
          Net secured_signal_13495: 30 loads, 30 SLICEs
          Net secured_signal_13541: 30 loads, 30 SLICEs
          Net secured_signal_13781: 48 loads, 48 SLICEs
          Net secured_signal_13788: 50 loads, 50 SLICEs
          Net secured_signal_13795: 5 loads, 5 SLICEs
          Net secured_signal_13800: 50 loads, 50 SLICEs
          Net secured_signal_13801: 50 loads, 50 SLICEs
          Net secured_signal_13802: 49 loads, 49 SLICEs
          Net secured_signal_13832: 1 loads, 1 SLICEs
          Net secured_signal_13867: 1 loads, 1 SLICEs
          Net secured_signal_14524: 2 loads, 2 SLICEs
          Net secured_signal_14527: 32 loads, 32 SLICEs
          Net secured_signal_14560: 1 loads, 1 SLICEs
          Net secured_signal_14627: 1 loads, 1 SLICEs
          Net secured_signal_14657: 11 loads, 11 SLICEs
          Net secured_signal_14695: 32 loads, 32 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.s_cdc_psel_w: 2 loads, 2 SLICEs
          Net secured_signal_14739: 16 loads, 0 SLICEs
          Net secured_signal_14740: 16 loads, 0 SLICEs
          Net secured_signal_14830: 1 loads, 1 SLICEs
          Net secured_signal_14908: 1 loads, 1 SLICEs
          Net secured_signal_14911: 1 loads, 1 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.srst_n: 1 loads, 1 SLICEs
          Net secured_signal_15466: 7 loads, 7 SLICEs
          Net secured_signal_15947: 5 loads, 5 SLICEs
          Net secured_signal_16137: 5 loads, 5 SLICEs
          Net secured_signal_16279: 5 loads, 5 SLICEs
          Net secured_signal_16298: 5 loads, 5 SLICEs
          Net secured_signal_17045: 25 loads, 25 SLICEs
          Net secured_signal_17047: 19 loads, 19 SLICEs
          Net secured_signal_17076: 25 loads, 25 SLICEs
          Net secured_signal_17078: 19 loads, 19 SLICEs
          Net secured_signal_17146: 26 loads, 26 SLICEs
          Net secured_signal_17154: 26 loads, 26 SLICEs
          Net secured_signal_17193: 26 loads, 26 SLICEs
          Net secured_signal_17233: 26 loads, 26 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.sclk_o_enable_1228: 1 loads, 1 SLICEs
          Net secured_signal_17410: 1 loads, 1 SLICEs
          Net secured_signal_17445: 1 loads, 1 SLICEs
          Net secured_signal_17478: 1 loads, 1 SLICEs
          Net secured_signal_17579: 1 loads, 1 SLICEs
          Net secured_signal_17582: 1 loads, 1 SLICEs
          Net secured_signal_17589: 1 loads, 1 SLICEs
          Net secured_signal_17917: 5 loads, 5 SLICEs
          Net secured_signal_17918: 5 loads, 5 SLICEs
          Net secured_signal_17932: 11 loads, 11 SLICEs
          Net secured_signal_17941: 5 loads, 5 SLICEs
          Net secured_signal_17943: 5 loads, 5 SLICEs
          Net secured_signal_17950: 11 loads, 11 SLICEs
          Net secured_signal_17952: 11 loads, 11 SLICEs
          Net secured_signal_17954: 11 loads, 11 SLICEs
          Net secured_signal_18118: 5 loads, 5 SLICEs
          Net secured_signal_18127: 5 loads, 5 SLICEs
          Net secured_signal_18248: 5 loads, 5 SLICEs
          Net secured_signal_18252: 5 loads, 5 SLICEs
          Net secured_signal_18671: 16 loads, 16 SLICEs
          Net secured_signal_18675: 25 loads, 25 SLICEs
          Net secured_signal_18676: 19 loads, 19 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.sclk_o_enable_959: 25 loads, 25 SLICEs
          Net secured_signal_18685: 1 loads, 1 SLICEs
          Net secured_signal_18697: 16 loads, 16 SLICEs
          Net secured_signal_18700: 25 loads, 25 SLICEs
          Net secured_signal_18701: 19 loads, 19 SLICEs
          Net secured_signal_18702: 16 loads, 16 SLICEs
          Net secured_signal_18703: 25 loads, 25 SLICEs
          Net secured_signal_18706: 19 loads, 19 SLICEs
          Net secured_signal_18709: 16 loads, 16 SLICEs
          Net secured_signal_18711: 25 loads, 25 SLICEs
          Net secured_signal_18713: 19 loads, 19 SLICEs
          Net secured_signal_18754: 1 loads, 1 SLICEs
          Net secured_signal_18756: 1 loads, 1 SLICEs
          Net secured_signal_18758: 1 loads, 1 SLICEs
          Net secured_signal_18883: 1 loads, 1 SLICEs
          Net secured_signal_19074: 25 loads, 25 SLICEs
          Net secured_signal_19078: 19 loads, 19 SLICEs
          Net secured_signal_19080: 19 loads, 19 SLICEs
          Net secured_signal_19081: 25 loads, 25 SLICEs
          Net secured_signal_19690: 1 loads, 1 SLICEs
          Net secured_signal_19693: 1 loads, 1 SLICEs
          Net secured_signal_19805: 26 loads, 26 SLICEs
          Net secured_signal_19807: 7 loads, 7 SLICEs
          Net secured_signal_19854: 7 loads, 7 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.rd_rsp_valid: 40 loads, 40 SLICEs
          Net secured_signal_20651: 3 loads, 3 SLICEs
          Net secured_signal_20746: 8 loads, 8 SLICEs
          Net secured_signal_20772: 8 loads, 8 SLICEs
          Net secured_signal_20794: 26 loads, 26 SLICEs
          Net secured_signal_20961: 1 loads, 1 SLICEs
          Net secured_signal_21608: 16 loads, 16 SLICEs
          Net secured_signal_21665: 16 loads, 16 SLICEs
          Net secured_signal_21707: 16 loads, 16 SLICEs
          Net secured_signal_21724: 16 loads, 16 SLICEs
          Net secured_signal_21742: 16 loads, 16 SLICEs
          Net secured_signal_21768: 16 loads, 16 SLICEs
          Net secured_signal_21798: 16 loads, 16 SLICEs
          Net secured_signal_21807: 16 loads, 16 SLICEs
          Net secured_signal_21827: 3 loads, 3 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.sclk_o_enable_900: 4 loads, 4 SLICEs
          Net secured_signal_23865: 14 loads, 14 SLICEs
          Net secured_signal_23895: 1 loads, 1 SLICEs
          Net secured_signal_24098: 1 loads, 1 SLICEs
          Net secured_signal_24240: 3 loads, 3 SLICEs
          Net secured_signal_24259: 16 loads, 16 SLICEs
          Net secured_signal_24285: 4 loads, 4 SLICEs
          Net secured_signal_24305: 1 loads, 1 SLICEs
          Net secured_signal_24458: 17 loads, 17 SLICEs
          Net secured_signal_24459: 5 loads, 5 SLICEs
          Net secured_signal_24461: 1 loads, 1 SLICEs
          Net secured_signal_24462: 1 loads, 1 SLICEs
          Net secured_signal_24493: 10 loads, 10 SLICEs
          Net secured_signal_24525: 9 loads, 9 SLICEs
          Net secured_signal_24586: 1 loads, 1 SLICEs
          Net secured_signal_24640: 10 loads, 10 SLICEs
          Net secured_signal_24654: 1 loads, 1 SLICEs
          Net secured_signal_24661: 1 loads, 1 SLICEs
          Net secured_signal_24728: 1 loads, 1 SLICEs
          Net secured_signal_25135: 8 loads, 8 SLICEs
          Net secured_signal_25428: 1 loads, 1 SLICEs
          Net secured_signal_25453: 3 loads, 3 SLICEs
          Net secured_signal_26114: 3 loads, 3 SLICEs
          Net secured_signal_26455: 3 loads, 3 SLICEs
          Net secured_signal_26793: 3 loads, 3 SLICEs
          Net secured_signal_26804: 1 loads, 1 SLICEs
          Net secured_signal_27177: 5 loads, 5 SLICEs
          Net secured_signal_27387: 5 loads, 5 SLICEs
          Net secured_signal_27913: 5 loads, 5 SLICEs
          Net secured_signal_28293: 5 loads, 5 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.i_apb_cdc.sclk_o_enable_859: 44 loads, 44
         SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.i_apb_cdc.s_rdata_valid_w: 32 loads, 32
         SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.i_apb_cdc.sclk_o_enable_1671: 32 loads, 32
         SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.i_apb_cdc.sclk_o_enable_857: 1 loads, 1
         SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_685: 16
         loads, 16 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_399: 2
         loads, 2 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_528: 2
         loads, 2 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_414: 8
         loads, 8 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_422: 8
         loads, 8 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_430: 8
         loads, 8 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_438: 8
         loads, 8 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_446: 8
         loads, 8 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_454: 8
         loads, 8 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_462: 8
         loads, 8 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_470: 8
         loads, 8 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_478: 8
         loads, 8 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_486: 8
         loads, 8 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_494: 8
         loads, 8 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_502: 8
         loads, 8 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_510: 8
         loads, 8 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_518: 8
         loads, 8 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_526: 8
         loads, 8 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_406: 8
         loads, 8 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_538: 5
         loads, 5 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_580: 4
         loads, 4 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_585: 2
         loads, 2 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_577: 4
         loads, 4 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.rd_fifo_en_w: 4 loads,
         4 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_20: 3
         loads, 3 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_574: 4
         loads, 4 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.u_rsp_fifo.u_fifo.clk_w
         _enable_583: 4 loads, 4 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fif
         o_dc.sclk_o_enable_1167: 74 loads, 74 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fif
         o_dc.clk_w_enable_589: 4 loads, 4 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_ctrl_fifo.u_fif
         o_dc.sclk_o_enable_902: 2 loads, 2 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.clk_w_enable_631: 2
         loads, 2 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.clk_w_enable_389: 2
         loads, 2 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.clk_w_enable_384: 48
         loads, 48 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.sclk_o_e
         nable_576: 12 loads, 12 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.sclk_o_e
         nable_566: 12 loads, 12 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.sclk_o_e
         nable_552: 12 loads, 12 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.sclk_o_e
         nable_538: 12 loads, 12 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.sclk_o_e
         nable_529: 12 loads, 12 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.sclk_o_e
         nable_518: 12 loads, 12 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.sclk_o_e
         nable_1676: 6 loads, 6 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.enable_b
         us_d: 8 loads, 8 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.sclk_o_e
         nable_210: 12 loads, 12 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.clk_w_en
         able_597: 9 loads, 9 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.rdata_ou
         t_en_rep2: 64 loads, 64 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.rdata_ou
         t_en_rep1: 64 loads, 64 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.sclk_o_e
         nable_54: 12 loads, 12 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.clk_w_en
         able_820: 11 loads, 11 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.clk_w_en
         able_611: 8 loads, 8 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.ASYNC.u_ctrl_fifo.u_fif
         o_dc.sclk_o_enable_184: 2 loads, 2 SLICEs
          Net kitcar_inst2.enable: 3 loads, 3 SLICEs
       Number of LSRs:  67
          Net axi_wstrb_i[0]: 3 loads, 0 SLICEs
          Net u_tragen.n71865: 25 loads, 25 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.n159553: 1 loads, 1 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.n71978: 7 loads, 7 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.n71959: 20 loads, 20 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.n33633: 16 loads, 16 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.n33645: 16 loads, 16 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.n156751: 1 loads, 1 SLICEs
          Net u_tragen.cpu0_inst.i_cpu.n159544: 1 loads, 1 SLICEs
          Net u_tragen.cpu0_inst.rst_w: 30 loads, 30 SLICEs
          Net u_tragen.cpu0_inst.n176011: 22 loads, 22 SLICEs
          Net u_tragen.cpu0_inst.n176046: 50 loads, 50 SLICEs
          Net u_tragen.cpu0_inst_system_resetn_o_net: 1042 loads, 1010 SLICEs
          Net sreset_n: 35 loads, 35 SLICEs
          Net areset_n_i: 1093 loads, 1093 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_wr.u_a2d_fifo.lscc_fifo_inst.fifo0._F
         ABRIC.u_fifo.wr_fifo_en_w: 3 loads, 3 SLICEs
          Net u_tragen.axi_tragen_inst.u_axi_m_rd.u_a2d_fifo.lscc_fifo_inst.fifo0._F
         ABRIC.u_fifo.wr_fifo_en_w: 3 loads, 3 SLICEs
          Pin rstn_i: 10 loads, 10 SLICEs (Net: cmos_xclr_c_c)
          Net arst_w: 3 loads, 3 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.s_cpu_rst_n_o: 2 loads, 2 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.combined_rst_n: 4 loads, 4 SLICEs
          Net cmos_xclr_c_c_N_13288: 2 loads, 0 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.sync_rst_n: 42 loads, 41 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.u_lp4mem.rst_w: 50 loads, 0 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.dq_out_adj_load_n_w[7]: 20 loads, 0 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.dq_in_adj_load_n_w[7]: 16 loads, 0 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.rd_load_n_w[0]: 2 loads, 0 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.wr_load_n_w[0]: 2 loads, 0 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.wrlvl_load_n_w[0]: 2 loads, 0 SLICEs
          Net
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u1_mem_sync.sync_reset: 10
         loads, 10 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.dll_rst_w: 1 loads, 0
         SLICEs
          Net
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.CA_GRP_ENA.u_ca_grp.ck_adj_load_n_r: 2
         loads, 0 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.cs_adj_load_n_w[0]: 1 loads, 0 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.ca_adj_load_n_w: 6 loads, 0 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.phy_srst_n: 930 loads, 930 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.u_lp4mem.CA_GRP_ENA.u_ca_grp.n31073: 5
         loads, 5 SLICEs
          Net secured_signal_11127: 1 loads, 1 SLICEs
          Net secured_signal_11469: 16 loads, 16 SLICEs
          Net secured_signal_11651: 8 loads, 8 SLICEs
          Net secured_signal_12125: 3 loads, 3 SLICEs
          Net secured_signal_12237: 32 loads, 32 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.p_cpu_rst_n_i: 155 loads, 123 SLICEs
          Net secured_signal_12855: 1 loads, 1 SLICEs
          Net secured_signal_12937: 25 loads, 25 SLICEs
          Net secured_signal_13423: 1 loads, 1 SLICEs
          Net secured_signal_13483: 16 loads, 16 SLICEs
          Net secured_signal_13484: 16 loads, 16 SLICEs
          Net secured_signal_13846: 20 loads, 20 SLICEs
          Net secured_signal_13847: 1 loads, 1 SLICEs
          Net secured_signal_13848: 7 loads, 7 SLICEs
          Net preset_n_i: 305 loads, 305 SLICEs
          Net secured_signal_14799: 2 loads, 2 SLICEs
          Net secured_signal_14820: 1 loads, 1 SLICEs
          Net secured_signal_14827: 2 loads, 2 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.srst_n: 4199 loads, 4181 SLICEs
          Net secured_signal_15468: 16 loads, 16 SLICEs
          Net secured_signal_19901: 8 loads, 8 SLICEs
          Net secured_signal_19902: 8 loads, 8 SLICEs
          Net secured_signal_19903: 8 loads, 8 SLICEs
          Net secured_signal_19904: 8 loads, 8 SLICEs
          Net secured_signal_28745: 4 loads, 4 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.clk_w_enable_585: 12
         loads, 12 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.arst_n: 733 loads, 733 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.wr_fifo_en_w_adj_14640:
         2 loads, 2 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_wr.ASYNC.u_data_fifo.u_fif
         o_dc.clk_w_enable_589: 37 loads, 37 SLICEs
          Net u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.clk_w_enable_389: 13
         loads, 13 SLICEs
          Net
         u_mem.lscc_lpddr4_mc_inst.AXI_BI.u_axi_if.u_rd.u_reorder_buff.dpram_wr: 6
         loads, 6 SLICEs
       Top 10 highest fanout non-clock nets:
          Net u_mem.lscc_lpddr4_mc_inst.srst_n: 4229 loads
          Net u_tragen.bridge_sm_nxt_r[3]: 2005 loads
          Net areset_n_i: 1096 loads
          Net u_tragen.cpu0_inst_system_resetn_o_net: 1050 loads
          Net u_mem.lscc_lpddr4_mc_inst.phy_srst_n: 933 loads
          Net u_mem.lscc_lpddr4_mc_inst.arst_n: 733 loads
          Net secured_signal_9971: 407 loads
          Net secured_signal_17225: 344 loads
          Net preset_n_i: 305 loads
          Net axi_wstrb_i[0]: 221 loads

       Number of warnings:  136
       Number of errors:    0

    Design Errors/Warnings

    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (57) : No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_
         ctrl_fifo/u_fifo_dc/*wp_sync1_r*[0].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_
         axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[0].ff_inst'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (58) : No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_
         ctrl_fifo/u_fifo_dc/*wp_sync1_r*[1].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_
         axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[1].ff_inst'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (59) : No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_
         ctrl_fifo/u_fifo_dc/*wp_sync1_r*[2].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_
         axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[2].ff_inst'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (60) : No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_
         ctrl_fifo/u_fifo_dc/*wp_sync1_r*[0].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_
         axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[0].ff_inst'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (61) : No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_
         ctrl_fifo/u_fifo_dc/*wp_sync1_r*[1].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_
         axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[1].ff_inst'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (62) : No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_
         ctrl_fifo/u_fifo_dc/*wp_sync1_r*[2].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_
         axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[2].ff_inst'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (63) : No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_
         data_fifo/u_fifo_dc/*wp_sync1_r*[0].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_
         axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync2_r*[0].ff_inst'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (64) : No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_
         data_fifo/u_fifo_dc/*wp_sync1_r*[1].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_
         axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync2_r*[1].ff_inst'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (65) : No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_
         data_fifo/u_fifo_dc/*wp_sync1_r*[2].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_
         axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync2_r*[2].ff_inst'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (66) : No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_
         data_fifo/u_fifo_dc/*wp_sync1_r*[3].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_
         axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync2_r*[3].ff_inst'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (70) : No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_
         ctrl_fifo/u_fifo_dc/*rp_sync1_r*[0].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_
         axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[0].ff_inst'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (71) : No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_
         ctrl_fifo/u_fifo_dc/*rp_sync1_r*[1].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_
         axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[1].ff_inst'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (72) : No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_
         ctrl_fifo/u_fifo_dc/*rp_sync1_r*[2].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_
         axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[2].ff_inst'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (73) : No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_
         ctrl_fifo/u_fifo_dc/*rp_sync1_r*[0].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_
         axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[0].ff_inst'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (74) : No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_
         ctrl_fifo/u_fifo_dc/*rp_sync1_r*[1].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_
         axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[1].ff_inst'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (75) : No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_
         ctrl_fifo/u_fifo_dc/*rp_sync1_r*[2].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_
         axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[2].ff_inst'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (76) : No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_
         data_fifo/u_fifo_dc/*rp_sync1_r*[0].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_
         axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync2_r*[0].ff_inst'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (77) : No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_
         data_fifo/u_fifo_dc/*rp_sync1_r*[1].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_
         axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync2_r*[1].ff_inst'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (78) : No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_
         data_fifo/u_fifo_dc/*rp_sync1_r*[2].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_
         axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync2_r*[2].ff_inst'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (79) : No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_
         data_fifo/u_fifo_dc/*rp_sync1_r*[3].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_
         axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync2_r*[3].ff_inst'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (85) : No pin matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_c
         trl_fifo/u_fifo_dc/mem*.*_inst/WDO*'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (86) : No pin matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_c
         trl_fifo/u_fifo_dc/mem*.*_inst/WDO*'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (87) : No pin matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_d
         ata_fifo/u_fifo_dc/mem*.*_inst/WDO*'.
    WARNING <1026001> - map: /media/d480/GitHubProjects/TssTechnique/TssProjects/Tss
         SemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/constraint_201.pdc
         (114) : No pin matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorde
         r_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/mem*.*_inst/WDO*'.
    WARNING <1027013> - map: No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/
         u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_r*[0].ff_inst */lscc_lpddr4_mc_i
         nst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[0].ff_ins
         t'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_r*[0].ff_inst */lscc_lpddr4
         _mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[0].f
         f_inst' in constraint 'ldc_create_group -name mc_rd_ctrl_wp_sync_b0 -bbox
         {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_f
         ifo/u_fifo_dc/*wp_sync1_r*[0].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if
         /u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[0].ff_inst}]'.
    WARNING <1027013> - map: No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/
         u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_r*[1].ff_inst */lscc_lpddr4_mc_i
         nst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[1].ff_ins
         t'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_r*[1].ff_inst */lscc_lpddr4
         _mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[1].f
         f_inst' in constraint 'ldc_create_group -name mc_rd_ctrl_wp_sync_b1 -bbox
         {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_f
         ifo/u_fifo_dc/*wp_sync1_r*[1].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if
         /u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[1].ff_inst}]'.
    WARNING <1027013> - map: No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/
         u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_r*[2].ff_inst */lscc_lpddr4_mc_i
         nst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[2].ff_ins
         t'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_r*[2].ff_inst */lscc_lpddr4
         _mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[2].f
         f_inst' in constraint 'ldc_create_group -name mc_rd_ctrl_wp_sync_b2 -bbox
         {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_f
         ifo/u_fifo_dc/*wp_sync1_r*[2].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if
         /u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[2].ff_inst}]'.
    WARNING <1027013> - map: No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/
         u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_r*[0].ff_inst */lscc_lpddr4_mc_i
         nst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[0].ff_ins
         t'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_r*[0].ff_inst */lscc_lpddr4
         _mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[0].f
         f_inst' in constraint 'ldc_create_group -name mc_wr_ctrl_wp_sync_b0 -bbox
         {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_f
         ifo/u_fifo_dc/*wp_sync1_r*[0].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if
         /u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[0].ff_inst}]'.
    WARNING <1027013> - map: No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/
         u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_r*[1].ff_inst */lscc_lpddr4_mc_i
         nst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[1].ff_ins
         t'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_r*[1].ff_inst */lscc_lpddr4
         _mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[1].f
         f_inst' in constraint 'ldc_create_group -name mc_wr_ctrl_wp_sync_b1 -bbox
         {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_f
         ifo/u_fifo_dc/*wp_sync1_r*[1].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if
         /u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[1].ff_inst}]'.
    WARNING <1027013> - map: No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/
         u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_r*[2].ff_inst */lscc_lpddr4_mc_i
         nst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[2].ff_ins
         t'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_r*[2].ff_inst */lscc_lpddr4
         _mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[2].f
         f_inst' in constraint 'ldc_create_group -name mc_wr_ctrl_wp_sync_b2 -bbox
         {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_f
         ifo/u_fifo_dc/*wp_sync1_r*[2].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if
         /u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[2].ff_inst}]'.
    WARNING <1027013> - map: No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/
         u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync1_r*[0].ff_inst */lscc_lpddr4_mc_i
         nst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync2_r*[0].ff_ins
         t'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync1_r*[0].ff_inst */lscc_lpddr4
         _mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync2_r*[0].f
         f_inst' in constraint 'ldc_create_group -name mc_wr_data_wp_sync_b0 -bbox
         {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_f
         ifo/u_fifo_dc/*wp_sync1_r*[0].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if
         /u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync2_r*[0].ff_inst}]'.
    WARNING <1027013> - map: No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/
         u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync1_r*[1].ff_inst */lscc_lpddr4_mc_i
         nst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync2_r*[1].ff_ins
         t'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync1_r*[1].ff_inst */lscc_lpddr4
         _mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync2_r*[1].f
         f_inst' in constraint 'ldc_create_group -name mc_wr_data_wp_sync_b1 -bbox
         {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_f
         ifo/u_fifo_dc/*wp_sync1_r*[1].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if
         /u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync2_r*[1].ff_inst}]'.
    WARNING <1027013> - map: No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/
         u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync1_r*[2].ff_inst */lscc_lpddr4_mc_i
         nst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync2_r*[2].ff_ins
         t'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync1_r*[2].ff_inst */lscc_lpddr4
         _mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync2_r*[2].f
         f_inst' in constraint 'ldc_create_group -name mc_wr_data_wp_sync_b2 -bbox
         {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_f
         ifo/u_fifo_dc/*wp_sync1_r*[2].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if
         /u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync2_r*[2].ff_inst}]'.
    WARNING <1027013> - map: No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/
         u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync1_r*[3].ff_inst */lscc_lpddr4_mc_i
         nst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync2_r*[3].ff_ins
         t'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync1_r*[3].ff_inst */lscc_lpddr4
         _mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync2_r*[3].f
         f_inst' in constraint 'ldc_create_group -name mc_wr_data_wp_sync_b3 -bbox
         {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_f
         ifo/u_fifo_dc/*wp_sync1_r*[3].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if
         /u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync2_r*[3].ff_inst}]'.
    WARNING <1027013> - map: No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/
         u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_r*[0].ff_inst */lscc_lpddr4_mc_i
         nst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[0].ff_ins
         t'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_r*[0].ff_inst */lscc_lpddr4
         _mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[0].f
         f_inst' in constraint 'ldc_create_group -name mc_rd_ctrl_rp_sync_b0 -bbox
         {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_f
         ifo/u_fifo_dc/*rp_sync1_r*[0].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if
         /u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[0].ff_inst}]'.
    WARNING <1027013> - map: No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/
         u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_r*[1].ff_inst */lscc_lpddr4_mc_i
         nst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[1].ff_ins
         t'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_r*[1].ff_inst */lscc_lpddr4
         _mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[1].f
         f_inst' in constraint 'ldc_create_group -name mc_rd_ctrl_rp_sync_b1 -bbox
         {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_f
         ifo/u_fifo_dc/*rp_sync1_r*[1].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if
         /u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[1].ff_inst}]'.
    WARNING <1027013> - map: No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/
         u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_r*[2].ff_inst */lscc_lpddr4_mc_i
         nst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[2].ff_ins
         t'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_r*[2].ff_inst */lscc_lpddr4
         _mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[2].f
         f_inst' in constraint 'ldc_create_group -name mc_rd_ctrl_rp_sync_b2 -bbox
         {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_f
         ifo/u_fifo_dc/*rp_sync1_r*[2].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if
         /u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[2].ff_inst}]'.
    WARNING <1027013> - map: No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/
         u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_r*[0].ff_inst */lscc_lpddr4_mc_i
         nst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[0].ff_ins
         t'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_r*[0].ff_inst */lscc_lpddr4
         _mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[0].f
         f_inst' in constraint 'ldc_create_group -name mc_wr_ctrl_rp_sync_b0 -bbox
         {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_f
         ifo/u_fifo_dc/*rp_sync1_r*[0].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if
         /u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[0].ff_inst}]'.
    WARNING <1027013> - map: No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/
         u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_r*[1].ff_inst */lscc_lpddr4_mc_i
         nst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[1].ff_ins
         t'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_r*[1].ff_inst */lscc_lpddr4
         _mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[1].f
         f_inst' in constraint 'ldc_create_group -name mc_wr_ctrl_rp_sync_b1 -bbox
         {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_f
         ifo/u_fifo_dc/*rp_sync1_r*[1].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if
         /u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[1].ff_inst}]'.
    WARNING <1027013> - map: No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/
         u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_r*[2].ff_inst */lscc_lpddr4_mc_i
         nst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[2].ff_ins
         t'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_r*[2].ff_inst */lscc_lpddr4
         _mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[2].f
         f_inst' in constraint 'ldc_create_group -name mc_wr_ctrl_rp_sync_b2 -bbox
         {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_f
         ifo/u_fifo_dc/*rp_sync1_r*[2].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if
         /u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[2].ff_inst}]'.
    WARNING <1027013> - map: No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/
         u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync1_r*[0].ff_inst */lscc_lpddr4_mc_i
         nst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync2_r*[0].ff_ins
         t'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync1_r*[0].ff_inst */lscc_lpddr4
         _mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync2_r*[0].f
         f_inst' in constraint 'ldc_create_group -name mc_wr_data_rp_sync_b0 -bbox
         {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_f
         ifo/u_fifo_dc/*rp_sync1_r*[0].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if
         /u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync2_r*[0].ff_inst}]'.
    WARNING <1027013> - map: No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/
         u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync1_r*[1].ff_inst */lscc_lpddr4_mc_i
         nst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync2_r*[1].ff_ins
         t'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync1_r*[1].ff_inst */lscc_lpddr4
         _mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync2_r*[1].f
         f_inst' in constraint 'ldc_create_group -name mc_wr_data_rp_sync_b1 -bbox
         {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_f
         ifo/u_fifo_dc/*rp_sync1_r*[1].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if
         /u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync2_r*[1].ff_inst}]'.
    WARNING <1027013> - map: No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/
         u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync1_r*[2].ff_inst */lscc_lpddr4_mc_i
         nst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync2_r*[2].ff_ins
         t'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync1_r*[2].ff_inst */lscc_lpddr4
         _mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync2_r*[2].f
         f_inst' in constraint 'ldc_create_group -name mc_wr_data_rp_sync_b2 -bbox
         {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_f
         ifo/u_fifo_dc/*rp_sync1_r*[2].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if
         /u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync2_r*[2].ff_inst}]'.
    WARNING <1027013> - map: No cell matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/
         u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync1_r*[3].ff_inst */lscc_lpddr4_mc_i
         nst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync2_r*[3].ff_ins
         t'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync1_r*[3].ff_inst */lscc_lpddr4
         _mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync2_r*[3].f
         f_inst' in constraint 'ldc_create_group -name mc_wr_data_rp_sync_b3 -bbox
         {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_f
         ifo/u_fifo_dc/*rp_sync1_r*[3].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if
         /u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync2_r*[3].ff_inst}]'.
    WARNING <1027013> - map: No pin matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u
         _rd/ASYNC.u_ctrl_fifo/u_fifo_dc/mem*.*_inst/WDO*'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/mem*.*_inst/WDO*' in constraint
         'set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/A
         SYNC.u_ctrl_fifo/u_fifo_dc/mem*.*_inst/WDO*] -datapath_only 4'.
    WARNING <1027013> - map: No pin matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u
         _wr/ASYNC.u_ctrl_fifo/u_fifo_dc/mem*.*_inst/WDO*'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/mem*.*_inst/WDO*' in constraint
         'set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/A
         SYNC.u_ctrl_fifo/u_fifo_dc/mem*.*_inst/WDO*] -datapath_only 4'.
    WARNING <1027013> - map: No pin matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u
         _wr/ASYNC.u_data_fifo/u_fifo_dc/mem*.*_inst/WDO*'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/mem*.*_inst/WDO*' in constraint
         'set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/A
         SYNC.u_data_fifo/u_fifo_dc/mem*.*_inst/WDO*] -datapath_only 4'.
    WARNING <1027013> - map: No pin matched '*/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u
         _rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/mem*.*_inst/WDO
         *'.
    WARNING <1014301> - map: Can't resolve object '*/lscc_lpddr4_mc_inst/AXI_BI.u_ax
         i_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/mem*.*_in
         st/WDO*' in constraint 'set_max_delay -from [get_pins */lscc_lpddr4_mc_inst
         /AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_in
         st/mem*.*_inst/WDO*] -datapath_only 4'.
    WARNING <1011001> - map: Remove invalid constraint 'ldc_create_group -name
         mc_rd_ctrl_wp_sync_b0 -bbox {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.
         u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_r*[0].ff_inst */lscc_lp
         ddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[
         0].ff_inst}]'.
    WARNING <1011001> - map: Remove invalid constraint 'ldc_create_group -name
         mc_rd_ctrl_wp_sync_b1 -bbox {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.
         u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_r*[1].ff_inst */lscc_lp
         ddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[
         1].ff_inst}]'.
    WARNING <1011001> - map: Remove invalid constraint 'ldc_create_group -name
         mc_rd_ctrl_wp_sync_b2 -bbox {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.
         u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_r*[2].ff_inst */lscc_lp
         ddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[
         2].ff_inst}]'.
    WARNING <1011001> - map: Remove invalid constraint 'ldc_create_group -name
         mc_wr_ctrl_wp_sync_b0 -bbox {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.
         u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_r*[0].ff_inst */lscc_lp
         ddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[
         0].ff_inst}]'.
    WARNING <1011001> - map: Remove invalid constraint 'ldc_create_group -name
         mc_wr_ctrl_wp_sync_b1 -bbox {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.
         u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_r*[1].ff_inst */lscc_lp
         ddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[
         1].ff_inst}]'.
    WARNING <1011001> - map: Remove invalid constraint 'ldc_create_group -name
         mc_wr_ctrl_wp_sync_b2 -bbox {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.
         u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_r*[2].ff_inst */lscc_lp
         ddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync2_r*[
         2].ff_inst}]'.
    WARNING <1011001> - map: Remove invalid constraint 'ldc_create_group -name
         mc_wr_data_wp_sync_b0 -bbox {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.
         u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync1_r*[0].ff_inst */lscc_lp
         ddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync2_r*[
         0].ff_inst}]'.
    WARNING <1011001> - map: Remove invalid constraint 'ldc_create_group -name
         mc_wr_data_wp_sync_b1 -bbox {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.
         u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync1_r*[1].ff_inst */lscc_lp
         ddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync2_r*[
         1].ff_inst}]'.
    WARNING <1011001> - map: Remove invalid constraint 'ldc_create_group -name
         mc_wr_data_wp_sync_b2 -bbox {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.
         u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync1_r*[2].ff_inst */lscc_lp
         ddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync2_r*[
         2].ff_inst}]'.
    WARNING <1011001> - map: Remove invalid constraint 'ldc_create_group -name
         mc_wr_data_wp_sync_b3 -bbox {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.
         u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync1_r*[3].ff_inst */lscc_lp
         ddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync2_r*[
         3].ff_inst}]'.
    WARNING <1011001> - map: Remove invalid constraint 'ldc_create_group -name
         mc_rd_ctrl_rp_sync_b0 -bbox {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.
         u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_r*[0].ff_inst */lscc_lp
         ddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[
         0].ff_inst}]'.
    WARNING <1011001> - map: Remove invalid constraint 'ldc_create_group -name
         mc_rd_ctrl_rp_sync_b1 -bbox {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.
         u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_r*[1].ff_inst */lscc_lp
         ddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[
         1].ff_inst}]'.
    WARNING <1011001> - map: Remove invalid constraint 'ldc_create_group -name
         mc_rd_ctrl_rp_sync_b2 -bbox {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.
         u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_r*[2].ff_inst */lscc_lp
         ddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[
         2].ff_inst}]'.
    WARNING <1011001> - map: Remove invalid constraint 'ldc_create_group -name
         mc_wr_ctrl_rp_sync_b0 -bbox {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.
         u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_r*[0].ff_inst */lscc_lp
         ddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[
         0].ff_inst}]'.
    WARNING <1011001> - map: Remove invalid constraint 'ldc_create_group -name
         mc_wr_ctrl_rp_sync_b1 -bbox {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.
         u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_r*[1].ff_inst */lscc_lp
         ddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[
         1].ff_inst}]'.
    WARNING <1011001> - map: Remove invalid constraint 'ldc_create_group -name
         mc_wr_ctrl_rp_sync_b2 -bbox {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.
         u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_r*[2].ff_inst */lscc_lp
         ddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync2_r*[
         2].ff_inst}]'.
    WARNING <1011001> - map: Remove invalid constraint 'ldc_create_group -name
         mc_wr_data_rp_sync_b0 -bbox {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.
         u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync1_r*[0].ff_inst */lscc_lp
         ddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync2_r*[
         0].ff_inst}]'.
    WARNING <1011001> - map: Remove invalid constraint 'ldc_create_group -name
         mc_wr_data_rp_sync_b1 -bbox {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.
         u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync1_r*[1].ff_inst */lscc_lp
         ddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync2_r*[
         1].ff_inst}]'.
    WARNING <1011001> - map: Remove invalid constraint 'ldc_create_group -name
         mc_wr_data_rp_sync_b2 -bbox {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.
         u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync1_r*[2].ff_inst */lscc_lp
         ddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync2_r*[
         2].ff_inst}]'.
    WARNING <1011001> - map: Remove invalid constraint 'ldc_create_group -name
         mc_wr_data_rp_sync_b3 -bbox {1 1} [get_cells {*/lscc_lpddr4_mc_inst/AXI_BI.
         u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync1_r*[3].ff_inst */lscc_lp
         ddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync2_r*[
         3].ff_inst}]'.
    WARNING <1011001> - map: Remove invalid constraint 'set_max_delay -from
         [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fi
         fo_dc/mem*.*_inst/WDO*] -datapath_only 4'.
    WARNING <1011001> - map: Remove invalid constraint 'set_max_delay -from
         [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fi
         fo_dc/mem*.*_inst/WDO*] -datapath_only 4'.
    WARNING <1011001> - map: Remove invalid constraint 'set_max_delay -from
         [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fi
         fo_dc/mem*.*_inst/WDO*] -datapath_only 4'.
    WARNING <1011001> - map: Remove invalid constraint 'set_max_delay -from
         [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_ctrl_
         dpram/lscc_distributed_dpram_inst/mem*.*_inst/WDO*] -datapath_only 4'.
    CRITICAL <52281053> - map:  There is no set_clock_uncertainty constraint on the
         PLL clock output 'CLKOP' of instance 'u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_
         pll/gen_no_refclk_mon.u_PLL.PLL_inst'. Please see FPGA-AN-02059-1.0 -
         Lattice Radiant Timing Constraints Methodology for further details.
    CRITICAL <52281053> - map:  There is no set_clock_uncertainty constraint on the
         PLL clock output 'CLKOS' of instance 'u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_
         pll/gen_no_refclk_mon.u_PLL.PLL_inst'. Please see FPGA-AN-02059-1.0 -
         Lattice Radiant Timing Constraints Methodology for further details.
    CRITICAL <52281053> - map:  There is no set_clock_uncertainty constraint on the
         PLL clock output 'CLKOP' of instance
         'ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst'.
         Please see FPGA-AN-02059-1.0 - Lattice Radiant Timing Constraints
         Methodology for further details.
    CRITICAL <52281053> - map:  There is no set_clock_uncertainty constraint on the
         PLL clock output 'CLKOS' of instance
         'ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst'.
         Please see FPGA-AN-02059-1.0 - Lattice Radiant Timing Constraints
         Methodology for further details.
    WARNING <52331043> - map: Port
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQS[0].u_DQS_BB is
         controlled by IVREF, property BANK_VREF is changed to 'OFF' from '1.1'.
    WARNING <52331043> - map: Port
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQS[1].u_DQS_BB is
         controlled by IVREF, property BANK_VREF is changed to 'OFF' from '1.1'.
    WARNING <52331043> - map: Port
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[0].u_DQ_BB is controlled
         by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
    WARNING <52331043> - map: Port
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[1].u_DQ_BB is controlled
         by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
    WARNING <52331043> - map: Port
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[2].u_DQ_BB is controlled
         by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
    WARNING <52331043> - map: Port
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[3].u_DQ_BB is controlled
         by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
    WARNING <52331043> - map: Port
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[4].u_DQ_BB is controlled
         by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
    WARNING <52331043> - map: Port
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[5].u_DQ_BB is controlled
         by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
    WARNING <52331043> - map: Port
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[6].u_DQ_BB is controlled
         by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
    WARNING <52331043> - map: Port
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[7].u_DQ_BB is controlled
         by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
    WARNING <52331043> - map: Port
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[8].u_DQ_BB is controlled
         by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
    WARNING <52331043> - map: Port
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[9].u_DQ_BB is controlled
         by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
    WARNING <52331043> - map: Port
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[10].u_DQ_BB is controlled
         by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
    WARNING <52331043> - map: Port
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[11].u_DQ_BB is controlled
         by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
    WARNING <52331043> - map: Port
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[12].u_DQ_BB is controlled
         by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
    WARNING <52331043> - map: Port
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[13].u_DQ_BB is controlled
         by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
    WARNING <52331043> - map: Port
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[14].u_DQ_BB is controlled
         by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
    WARNING <52331043> - map: Port
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[15].u_DQ_BB is controlled
         by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
    WARNING <52331043> - map: Port
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DMI[0].u_DQ_BB is controlled
         by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
    WARNING <52331043> - map: Port
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DMI[1].u_DQ_BB is controlled
         by IVREF, property BANK_VREF is changed to 'REF_INT' from '1.1'.
    WARNING <52331031> - map: Tristate DDR
         'u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.TS[0].TS_X4.u_TSHX4DQ$r0'
         is replicated for
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[0].u_DQ_BB.
    WARNING <52331031> - map: Tristate DDR
         'u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.TS[0].TS_X4.u_TSHX4DQ$r1'
         is replicated for
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[1].u_DQ_BB.
    WARNING <52331031> - map: Tristate DDR
         'u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.TS[0].TS_X4.u_TSHX4DQ$r2'
         is replicated for
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[2].u_DQ_BB.
    WARNING <52331031> - map: Tristate DDR
         'u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.TS[0].TS_X4.u_TSHX4DQ$r3'
         is replicated for
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[3].u_DQ_BB.
    WARNING <52331031> - map: Tristate DDR
         'u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.TS[0].TS_X4.u_TSHX4DQ$r4'
         is replicated for
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[4].u_DQ_BB.
    WARNING <52331031> - map: Tristate DDR
         'u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.TS[0].TS_X4.u_TSHX4DQ$r5'
         is replicated for
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[5].u_DQ_BB.
    WARNING <52331031> - map: Tristate DDR
         'u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.TS[0].TS_X4.u_TSHX4DQ$r6'
         is replicated for
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[6].u_DQ_BB.
    WARNING <52331031> - map: Tristate DDR
         'u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.TS[0].TS_X4.u_TSHX4DQ$r7'
         is replicated for
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[7].u_DQ_BB.
    WARNING <52331031> - map: Tristate DDR
         'u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.TS[1].TS_X4.u_TSHX4DQ$r8'
         is replicated for
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[8].u_DQ_BB.
    WARNING <52331031> - map: Tristate DDR
         'u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.TS[1].TS_X4.u_TSHX4DQ$r9'
         is replicated for
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[9].u_DQ_BB.
    WARNING <52331031> - map: Tristate DDR
         'u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.TS[1].TS_X4.u_TSHX4DQ$r10'
         is replicated for
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[10].u_DQ_BB.
    WARNING <52331031> - map: Tristate DDR
         'u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.TS[1].TS_X4.u_TSHX4DQ$r11'
         is replicated for
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[11].u_DQ_BB.
    WARNING <52331031> - map: Tristate DDR
         'u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.TS[1].TS_X4.u_TSHX4DQ$r12'
         is replicated for
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[12].u_DQ_BB.
    WARNING <52331031> - map: Tristate DDR
         'u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.TS[1].TS_X4.u_TSHX4DQ$r13'
         is replicated for
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[13].u_DQ_BB.
    WARNING <52331031> - map: Tristate DDR
         'u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.TS[1].TS_X4.u_TSHX4DQ$r14'
         is replicated for
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[14].u_DQ_BB.
    WARNING <52331031> - map: Tristate DDR
         'u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.TS[1].TS_X4.u_TSHX4DQ$r15'
         is replicated for
         u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.DQ[15].u_DQ_BB.

    IO (PIO) Attributes

    +---------------------+-----------+-----------+-------+-------+-----------+
    | IO Name             | Direction | Levelmode |  IO   |  IO   | Special   |
    |                     |           |  IO_TYPE  |  REG  |  DDR  | IO Buffer |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | LED[1]              | BIDIR     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | LED[0]              | BIDIR     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | LED[2]              | BIDIR     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | LED[3]              | BIDIR     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | LED[4]              | BIDIR     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | LED[5]              | BIDIR     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | LED[6]              | BIDIR     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | LED[7]              | BIDIR     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | LED[8]              | BIDIR     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | LED[9]              | BIDIR     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | LED[10]             | BIDIR     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | LED[11]             | BIDIR     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_dqs_io[0]       | BIDIR     | LVSTLD_I  |       | O/T   |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_dqs_io[1]       | BIDIR     | LVSTLD_I  |       | O/T   |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_dq_io[0]        | BIDIR     | LVSTL_I   |       | I/O   |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_dq_io[1]        | BIDIR     | LVSTL_I   |       | I/O   |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_dq_io[2]        | BIDIR     | LVSTL_I   |       | I/O   |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_dq_io[3]        | BIDIR     | LVSTL_I   |       | I/O   |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_dq_io[4]        | BIDIR     | LVSTL_I   |       | I/O   |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_dq_io[5]        | BIDIR     | LVSTL_I   |       | I/O   |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_dq_io[6]        | BIDIR     | LVSTL_I   |       | I/O   |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_dq_io[7]        | BIDIR     | LVSTL_I   |       | I/O   |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_dq_io[8]        | BIDIR     | LVSTL_I   |       | I/O   |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_dq_io[9]        | BIDIR     | LVSTL_I   |       | I/O   |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_dq_io[10]       | BIDIR     | LVSTL_I   |       | I/O   |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_dq_io[11]       | BIDIR     | LVSTL_I   |       | I/O   |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_dq_io[12]       | BIDIR     | LVSTL_I   |       | I/O   |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_dq_io[13]       | BIDIR     | LVSTL_I   |       | I/O   |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_dq_io[14]       | BIDIR     | LVSTL_I   |       | I/O   |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_dq_io[15]       | BIDIR     | LVSTL_I   |       | I/O   |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_dmi_io[0]       | BIDIR     | LVSTL_I   |       | O     |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_dmi_io[1]       | BIDIR     | LVSTL_I   |       | O     |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_ck_o[0]         | OUTPUT    | LVSTLD_I  |       | O     |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_cke_o[0]        | OUTPUT    | LVSTL_I   |       | O     |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_cs_o[0]         | OUTPUT    | LVSTL_I   |       | O     |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_ca_o[0]         | OUTPUT    | LVSTL_I   |       | O     |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_ca_o[1]         | OUTPUT    | LVSTL_I   |       | O     |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_ca_o[2]         | OUTPUT    | LVSTL_I   |       | O     |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_ca_o[3]         | OUTPUT    | LVSTL_I   |       | O     |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_ca_o[4]         | OUTPUT    | LVSTL_I   |       | O     |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_ca_o[5]         | OUTPUT    | LVSTL_I   |       | O     |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | init_done_o         | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | uart_txd_o          | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | fs[2]               | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | fs[1]               | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | fs[0]               | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | cmos_xclr           | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | mipi_clk            | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | out_clk0            | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | gnd_clk             | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | out_clk1            | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | sim_o               | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_odt_ca_o        | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | ddr_reset_n_o       | OUTPUT    | LVSTL_I   |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | clk_ext             | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rstn_i              | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | pll_refclk_i        | INPUT     | LVSTLD_I  |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | uart_rxd_i          | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+

    Removed logic

    Block u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/bridge_s1.bridge_s1/i1_2_lut_
         3_lut_4_lut_adj_5481 undriven or does not drive anything - clipped.
    Block u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/bridge_s1.bridge_s1/i68188_2_
         lut undriven or does not drive anything - clipped.
    Block u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/bridge_s1.bridge_s1/i1_4_lut_
         adj_5461 undriven or does not drive anything - clipped.
    Block u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/bridge_s1.bridge_s1/i1_2_lut_
         rep_5800_3_lut undriven or does not drive anything - clipped.
    Block u_tragen/i1_2_lut_3_lut_4_lut undriven or does not drive anything -
         clipped.
    Block u_tragen/i20_3_lut undriven or does not drive anything - clipped.
    Block GSR_INST undriven or does not drive anything - clipped.
    Block i2 was optimized away.
    Block u_tragen/i1_2_lut_adj_6235 was optimized away.
    Block gnd_clk_pad.vlo_inst was optimized away.
    Block u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/bridge_s1.bridge_s1/i2_3_lut_
         4_lut_adj_5485 was optimized away.
    Block u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/bridge_s1.bridge_s1/i1_3_lut_
         rep_4932_4_lut was optimized away.
    Block u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/bridge_s1.bridge_s1/bridge_sm
         _nxt_r_2__I_0_2_lut_3_lut_4_lut was optimized away.
    Block u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/bridge_s1.bridge_s1/i4_4_lut_
         adj_5463 was optimized away.
    Block u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/bridge_s1.bridge_s1/i1_4_lut_
         adj_5462 was optimized away.
    Block u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/bridge_s1.bridge_s1/i89_4_lut
         was optimized away.
    Block u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/bridge_s1.bridge_s1/i2_3_lut_
         4_lut was optimized away.
    Block u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/bridge_s1.bridge_s1/i119399_4
         _lut was optimized away.
    Block u_tragen/ahbl0_inst/lscc_ahbl_interconnect_inst/ahb_lite_bus.u_lscc_ahbl_b
         us/u_lscc_ahbl_multiplexor/i1_2_lut_3_lut_4_lut_adj_5493 was optimized
         away.
    Block u_tragen/ahbl0_inst/lscc_ahbl_interconnect_inst/ahb_lite_bus.u_lscc_ahbl_b
         us/u_lscc_ahbl_multiplexor/i1_2_lut_3_lut_4_lut was optimized away.
    Block u_tragen/ahbl0_inst/lscc_ahbl_interconnect_inst/ahb_lite_bus.u_lscc_ahbl_b
         us/u_lscc_ahbl_multiplexor/i1_2_lut_rep_4934_3_lut_4_lut was optimized
         away.
    Block u_tragen/i66930_2_lut_rep_4957_3_lut was optimized away.
    Block u_tragen/i1_2_lut_rep_5784 was optimized away.
    Block u_tragen/i1_2_lut_rep_4947_3_lut_4_lut was optimized away.
    Block u_tragen/i1_2_lut_rep_4945_3_lut_4_lut was optimized away.
    Block u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/arst_n_I_3466_1_lut was
         optimized away.
    Block u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/i312_2_lut_rep_6111 was
         optimized away.
    Block u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u1_mem_sync/i1_2_lut_3_lu
         t_4_lut_1_lut was optimized away.
    Block u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u1_mem_sync/i29_1_lut_rep
         _6210 was optimized away.
    Block u_mem/lscc_lpddr4_mc_inst/i48_1_lut was optimized away.
    Block u_tragen/apb0_inst/lscc_apb_interconnect_inst/apb_bus.u_lscc_apb_bus/u_lsc
         c_apb_multiplexor/cpu0_inst_system_resetn_o_net_I_0_1_lut_rep_6334 was
         optimized away.
    Block u_tragen/axi_tragen_inst/u_axi_m_wr/areset_n_i_I_0_1_lut was optimized
         away.
    Block u_tragen/axi_tragen_inst/u_axi_perf_calc/i51_1_lut was optimized away.
    Block u_tragen/gpio0_inst/lscc_gpio_inst/LxxNX.lscc_gpio_lmmi_0/direction_r_0__I
         _0_2_1_lut was optimized away.
    Block u_tragen/gpio0_inst/lscc_gpio_inst/LxxNX.lscc_gpio_lmmi_0/direction_r_9__I
         _0_2_1_lut_rep_6183 was optimized away.
    Block u_tragen/gpio0_inst/lscc_gpio_inst/LxxNX.lscc_gpio_lmmi_0/direction_r_8__I
         _0_2_1_lut_rep_6184 was optimized away.
    Block u_tragen/gpio0_inst/lscc_gpio_inst/LxxNX.lscc_gpio_lmmi_0/direction_r_7__I
         _0_2_1_lut_rep_6185 was optimized away.
    Block u_tragen/gpio0_inst/lscc_gpio_inst/LxxNX.lscc_gpio_lmmi_0/direction_r_6__I
         _0_2_1_lut_rep_6186 was optimized away.
    Block u_tragen/gpio0_inst/lscc_gpio_inst/LxxNX.lscc_gpio_lmmi_0/direction_r_5__I
         _0_2_1_lut_rep_6187 was optimized away.
    Block u_tragen/gpio0_inst/lscc_gpio_inst/LxxNX.lscc_gpio_lmmi_0/direction_r_4__I
         _0_2_1_lut_rep_6188 was optimized away.
    Block u_tragen/gpio0_inst/lscc_gpio_inst/LxxNX.lscc_gpio_lmmi_0/direction_r_3__I
         _0_2_1_lut_rep_6189 was optimized away.
    Block u_tragen/gpio0_inst/lscc_gpio_inst/LxxNX.lscc_gpio_lmmi_0/direction_r_2__I
         _0_2_1_lut_rep_6190 was optimized away.
    Block u_tragen/gpio0_inst/lscc_gpio_inst/LxxNX.lscc_gpio_lmmi_0/direction_r_1__I
         _0_2_1_lut_rep_6191 was optimized away.
    Block u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/bridge_s1.bridge_s1/i130895_2
         _lut was optimized away.
    Block u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/bridge_s1.bridge_s1/i3_4_lut_
         adj_5470 was optimized away.
    Block u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/bridge_s1.bridge_s1/i1_2_lut_
         4_lut was optimized away.
    Block u_tragen/ahbl0_inst/lscc_ahbl_interconnect_inst/ahb_lite_bus.u_lscc_ahbl_b
         us/u_lscc_ahbl_multiplexor/i1_2_lut_3_lut_4_lut_adj_5492 was optimized
         away.
    Block u_tragen/i2_3_lut_rep_4935_4_lut was optimized away.
    Block u_tragen/i1_2_lut_rep_4950_3_lut_4_lut was optimized away.
    Block u_tragen/i1_2_lut_rep_4944_3_lut_4_lut was optimized away.
    Block u_tragen/i1_2_lut_rep_4948_3_lut_4_lut was optimized away.
    Block u_tragen/i1_2_lut_rep_4949_3_lut_4_lut was optimized away.
    Block u_tragen/i1_3_lut was optimized away.
    Block i1_2_lut_adj_6241 was optimized away.
    Block u_tragen/i3_4_lut was optimized away.

    PLL/DLL Summary

    PLL 1:                                 Pin/Node Value
      PLL Instance Name:                            u_mem/lscc_lpddr4_mc_inst/u_lp4m
           em/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst
      Input Reference Clock:               PIN      pll_refclk_i_c
      Output Clock(P):                     NODE
           u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.fbclk_w
      Output Clock(S):                     NODE
           u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclk_w
      Output Clock(S2):                             NONE
      Output Clock(S3):                             NONE
      Output Clock(S4):                             NONE
      Output Clock(S5):                             NONE
      Feedback Signal:                     NODE
           u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.fbclk_w
      Reset Signal:                        NODE     cmos_xclr_c_c_N_13288
      Standby Signal:                      NODE     u_tragen.bridge_sm_nxt_r[3]
      PLL LOCK signal:                     NODE
           u_mem.lscc_lpddr4_mc_inst.u_lp4mem.pll_lock_o
      PLL Internal LOCK Signal:                     NONE
      A Divider:                                    15
      B Divider:                                    2
      C Divider:                                    7
      D Divider:                                    7
      E Divider:                                    7
      F Divider:                                    7
      A Post Divider Shift:                         15
      B Post Divider Shift:                         2
      C Post Divider Shift:                         7
      D Post Divider Shift:                         7
      E Post Divider Shift:                         7
      F Post Divider Shift:                         7
      A Section VCO Phase Shift:                    0
      B Section VCO Phase Shift:                    0
      C Section VCO Phase Shift:                    0
      D Section VCO Phase Shift:                    0
      E Section VCO Phase Shift:                    0
      F Section VCO Phase Shift:                    0
      CLKOP Trim Setting:                           0000
      CLKOS Trim Setting:                           0000
      CLKOS2 Trim Setting:                          0000
      CLKOS3 Trim Setting:                          0000
      CLKOS4 Trim Setting:                          0000
      CLKOS5 Trim Setting:                          0000
    PLL 2:                                 Pin/Node Value
      PLL Instance Name:                            ASYNC_AXI.u_aclk_pclk/lscc_pll_i
           nst/gen_no_refclk_mon.u_PLL.PLL_inst
      Input Reference Clock:               NODE     osc_clk_90
      Output Clock(P):                     NODE     clk_w
      Output Clock(S):                     PIN,NODE out_clk1_c
      Output Clock(S2):                             NONE
      Output Clock(S3):                             NONE
      Output Clock(S4):                             NONE
      Output Clock(S5):                             NONE
      Feedback Signal:                     NODE     clk_w
      Reset Signal:                        NODE     cmos_xclr_c_c_N_13288
      Standby Signal:                      NODE     u_tragen.bridge_sm_nxt_r[3]
      PLL LOCK signal:                     NODE     ASYNC_AXI.aclk_pll_lock
      PLL Internal LOCK Signal:                     NONE
      A Divider:                                    9
      B Divider:                                    14
      C Divider:                                    7
      D Divider:                                    7
      E Divider:                                    7
      F Divider:                                    7
      A Post Divider Shift:                         9
      B Post Divider Shift:                         14
      C Post Divider Shift:                         7
      D Post Divider Shift:                         7
      E Post Divider Shift:                         7
      F Post Divider Shift:                         7
      A Section VCO Phase Shift:                    0
      B Section VCO Phase Shift:                    0
      C Section VCO Phase Shift:                    0
      D Section VCO Phase Shift:                    0
      E Section VCO Phase Shift:                    0
      F Section VCO Phase Shift:                    0
      CLKOP Trim Setting:                           0000
      CLKOS Trim Setting:                           0000
      CLKOS2 Trim Setting:                          0000
      CLKOS3 Trim Setting:                          0000
      CLKOS4 Trim Setting:                          0000
      CLKOS5 Trim Setting:                          0000

    OSC Summary

    OSC 1:                                 Pin/Node Value
      OSC Instance Name:
           osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst
      Enable High Frequency SDSC:          NODE     axi_wstrb_i[0]
      High Frequency Output:               NODE     osc_clk_90
      Low Frequency Output:                         NONE
      SDC Output:                                   NONE
      High Frequency DIV:                           4

    ASIC Components

    Instance Name: u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/u_lscc_mem0/lifcl_LA
         TG1.ebr.dp.LIFCL.u_mem/mem_main/uinst_0/prim.NON_MIX.xADDR[0].xDATA[9].mem_
         file.u_mem0/LIFCL.dp16k.DP16K_MODE_inst
             Type: EBR_CORE
    Instance Name: u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/u_lscc_mem0/lifcl_LA
         TG1.ebr.dp.LIFCL.u_mem/mem_main/uinst_0/prim.NON_MIX.xADDR[0].xDATA[8].mem_
         file.u_mem0/LIFCL.dp16k.DP16K_MODE_inst
             Type: EBR_CORE
    Instance Name: u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/u_lscc_mem0/lifcl_LA
         TG1.ebr.dp.LIFCL.u_mem/mem_main/uinst_0/prim.NON_MIX.xADDR[0].xDATA[7].mem_
         file.u_mem0/LIFCL.dp16k.DP16K_MODE_inst
             Type: EBR_CORE
    Instance Name: u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/u_lscc_mem0/lifcl_LA
         TG1.ebr.dp.LIFCL.u_mem/mem_main/uinst_0/prim.NON_MIX.xADDR[0].xDATA[6].mem_
         file.u_mem0/LIFCL.dp16k.DP16K_MODE_inst
             Type: EBR_CORE
    Instance Name: u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/u_lscc_mem0/lifcl_LA
         TG1.ebr.dp.LIFCL.u_mem/mem_main/uinst_0/prim.NON_MIX.xADDR[0].xDATA[5].mem_
         file.u_mem0/LIFCL.dp16k.DP16K_MODE_inst
             Type: EBR_CORE
    Instance Name: u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/u_lscc_mem0/lifcl_LA
         TG1.ebr.dp.LIFCL.u_mem/mem_main/uinst_0/prim.NON_MIX.xADDR[0].xDATA[4].mem_
         file.u_mem0/LIFCL.dp16k.DP16K_MODE_inst
             Type: EBR_CORE
    Instance Name: u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/u_lscc_mem0/lifcl_LA
         TG1.ebr.dp.LIFCL.u_mem/mem_main/uinst_0/prim.NON_MIX.xADDR[0].xDATA[3].mem_
         file.u_mem0/LIFCL.dp16k.DP16K_MODE_inst
             Type: EBR_CORE
    Instance Name: u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/u_lscc_mem0/lifcl_LA
         TG1.ebr.dp.LIFCL.u_mem/mem_main/uinst_0/prim.NON_MIX.xADDR[0].xDATA[2].mem_
         file.u_mem0/LIFCL.dp16k.DP16K_MODE_inst
             Type: EBR_CORE
    Instance Name: u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/u_lscc_mem0/lifcl_LA
         TG1.ebr.dp.LIFCL.u_mem/mem_main/uinst_0/prim.NON_MIX.xADDR[0].xDATA[1].mem_
         file.u_mem0/LIFCL.dp16k.DP16K_MODE_inst
             Type: EBR_CORE
    Instance Name: u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/u_lscc_mem0/lifcl_LA
         TG1.ebr.dp.LIFCL.u_mem/mem_main/uinst_0/prim.NON_MIX.xADDR[0].xDATA[15].mem
         _file.u_mem0/LIFCL.dp16k.DP16K_MODE_inst
             Type: EBR_CORE
    Instance Name: u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/u_lscc_mem0/lifcl_LA
         TG1.ebr.dp.LIFCL.u_mem/mem_main/uinst_0/prim.NON_MIX.xADDR[0].xDATA[14].mem
         _file.u_mem0/LIFCL.dp16k.DP16K_MODE_inst
             Type: EBR_CORE
    Instance Name: u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/u_lscc_mem0/lifcl_LA
         TG1.ebr.dp.LIFCL.u_mem/mem_main/uinst_0/prim.NON_MIX.xADDR[0].xDATA[13].mem
         _file.u_mem0/LIFCL.dp16k.DP16K_MODE_inst
             Type: EBR_CORE
    Instance Name: u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/u_lscc_mem0/lifcl_LA
         TG1.ebr.dp.LIFCL.u_mem/mem_main/uinst_0/prim.NON_MIX.xADDR[0].xDATA[12].mem
         _file.u_mem0/LIFCL.dp16k.DP16K_MODE_inst
             Type: EBR_CORE
    Instance Name: u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/u_lscc_mem0/lifcl_LA
         TG1.ebr.dp.LIFCL.u_mem/mem_main/uinst_0/prim.NON_MIX.xADDR[0].xDATA[11].mem
         _file.u_mem0/LIFCL.dp16k.DP16K_MODE_inst
             Type: EBR_CORE
    Instance Name: u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/u_lscc_mem0/lifcl_LA
         TG1.ebr.dp.LIFCL.u_mem/mem_main/uinst_0/prim.NON_MIX.xADDR[0].xDATA[10].mem
         _file.u_mem0/LIFCL.dp16k.DP16K_MODE_inst
             Type: EBR_CORE
    Instance Name: u_tragen/IMPL.sysmem0_inst/lscc_sys_mem_inst/u_lscc_mem0/lifcl_LA
         TG1.ebr.dp.LIFCL.u_mem/mem_main/uinst_0/prim.NON_MIX.xADDR[0].xDATA[0].mem_
         file.u_mem0/LIFCL.dp16k.DP16K_MODE_inst
             Type: EBR_CORE
    Instance Name: osc_int_inst/lscc_osc_inst/u_OSC.OSCA_inst
             Type: OSC_CORE
    Instance Name:
         u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_pll/gen_no_refclk_mon.u_PLL.PLL_inst
             Type: PLL_CORE
    Instance Name: u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/DQSBUF[1].VREF.u0_
         DQSBUF.DQSBUFA_inst
             Type: DQSBUFA_CORE
    Instance Name: u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/DQSBUF[1].VREF.u0_
         DQSBUF.BNKVRGEN18_inst
             Type: IVREF_CORE
    Instance Name: u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/DQSBUF[0].VREF.u0_
         DQSBUF.DQSBUFA_inst
             Type: DQSBUFA_CORE
    Instance Name: u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u_dq_dqs_dm/DQSBUF[0].VREF.u0_
         DQSBUF.BNKVRGEN18_inst
             Type: IVREF_CORE
    Instance Name:
         u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKSYNC.ECLKSYNC_inst
             Type: ECLKSYNC_CORE
    Instance Name:
         u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_DDRDLL.DDRDLL_inst
             Type: DDRDLL_CORE
    Instance Name:
         u_mem/lscc_lpddr4_mc_inst/u_lp4mem/u1_clock_sync/u0_ECLKDIV.ECLKDIV_inst
             Type: ECLKDIV_CORE
    Instance Name: secured_comp_12231
             Type: EBR_CORE
    Instance Name: secured_comp_12233
             Type: EBR_CORE
    Instance Name: secured_comp_12234
             Type: EBR_CORE
    Instance Name: secured_comp_12235
             Type: EBR_CORE
    Instance Name: secured_comp_12236
             Type: EBR_CORE
    Instance Name: secured_comp_12238
             Type: EBR_CORE
    Instance Name: secured_comp_12239
             Type: EBR_CORE
    Instance Name: secured_comp_12240
             Type: EBR_CORE
    Instance Name: secured_comp_12242
             Type: EBR_CORE
    Instance Name: secured_comp_12243
             Type: EBR_CORE
    Instance Name: secured_comp_12244
             Type: EBR_CORE
    Instance Name: secured_comp_12245
             Type: EBR_CORE
    Instance Name: secured_comp_12247
             Type: EBR_CORE
    Instance Name: secured_comp_12248
             Type: EBR_CORE
    Instance Name: secured_comp_12249
             Type: EBR_CORE
    Instance Name: secured_comp_12250
             Type: EBR_CORE
    Instance Name: secured_comp_12520
             Type: EBR_CORE
    Instance Name: secured_comp_12521
             Type: EBR_CORE
    Instance Name: secured_comp_12522
             Type: EBR_CORE
    Instance Name: secured_comp_12523
             Type: EBR_CORE
    Instance Name: secured_comp_12524
             Type: EBR_CORE
    Instance Name: u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_l
         pddr4_mc_rd_rtrn_ebr_inst/lscc_ram_dp_inst/mem_main/NON_MIX.ADDR_ROUTE[0].D
         ATA_ROUTE[3].no_init.u_mem0/LIFCL_MEM.pdp16k.PDP16K_MODE_inst
             Type: EBR_CORE
    Instance Name: u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_l
         pddr4_mc_rd_rtrn_ebr_inst/lscc_ram_dp_inst/mem_main/NON_MIX.ADDR_ROUTE[0].D
         ATA_ROUTE[2].no_init.u_mem0/LIFCL_MEM.pdp16k.PDP16K_MODE_inst
             Type: EBR_CORE
    Instance Name: u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_l
         pddr4_mc_rd_rtrn_ebr_inst/lscc_ram_dp_inst/mem_main/NON_MIX.ADDR_ROUTE[0].D
         ATA_ROUTE[1].no_init.u_mem0/LIFCL_MEM.pdp16k.PDP16K_MODE_inst
             Type: EBR_CORE
    Instance Name: u_mem/lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_reorder_buff/u_l
         pddr4_mc_rd_rtrn_ebr_inst/lscc_ram_dp_inst/mem_main/NON_MIX.ADDR_ROUTE[0].D
         ATA_ROUTE[0].no_init.u_mem0/LIFCL_MEM.pdp16k.PDP16K_MODE_inst
             Type: EBR_CORE
    Instance Name:
         ASYNC_AXI.u_aclk_pclk/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst
             Type: PLL_CORE

    Constraint Summary

       Total number of constraints: 195
       Total number of constraints dropped: 24
       Dropped constraints are:
         ldc_create_group -name mc_rd_ctrl_wp_sync_b0 -bbox {1 1} [get_cells {*/lscc
         _lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_
         r*[0].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/
         u_fifo_dc/*wp_sync2_r*[0].ff_inst}]
         ldc_create_group -name mc_rd_ctrl_wp_sync_b1 -bbox {1 1} [get_cells {*/lscc
         _lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_
         r*[1].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/
         u_fifo_dc/*wp_sync2_r*[1].ff_inst}]
         ldc_create_group -name mc_rd_ctrl_wp_sync_b2 -bbox {1 1} [get_cells {*/lscc
         _lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_
         r*[2].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/
         u_fifo_dc/*wp_sync2_r*[2].ff_inst}]
         ldc_create_group -name mc_wr_ctrl_wp_sync_b0 -bbox {1 1} [get_cells {*/lscc
         _lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_
         r*[0].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/
         u_fifo_dc/*wp_sync2_r*[0].ff_inst}]
         ldc_create_group -name mc_wr_ctrl_wp_sync_b1 -bbox {1 1} [get_cells {*/lscc
         _lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_
         r*[1].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/
         u_fifo_dc/*wp_sync2_r*[1].ff_inst}]
         ldc_create_group -name mc_wr_ctrl_wp_sync_b2 -bbox {1 1} [get_cells {*/lscc
         _lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*wp_sync1_
         r*[2].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/
         u_fifo_dc/*wp_sync2_r*[2].ff_inst}]
         ldc_create_group -name mc_wr_data_wp_sync_b0 -bbox {1 1} [get_cells {*/lscc
         _lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync1_
         r*[0].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/
         u_fifo_dc/*wp_sync2_r*[0].ff_inst}]
         ldc_create_group -name mc_wr_data_wp_sync_b1 -bbox {1 1} [get_cells {*/lscc
         _lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync1_
         r*[1].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/
         u_fifo_dc/*wp_sync2_r*[1].ff_inst}]
         ldc_create_group -name mc_wr_data_wp_sync_b2 -bbox {1 1} [get_cells {*/lscc
         _lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync1_
         r*[2].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/
         u_fifo_dc/*wp_sync2_r*[2].ff_inst}]
         ldc_create_group -name mc_wr_data_wp_sync_b3 -bbox {1 1} [get_cells {*/lscc
         _lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*wp_sync1_
         r*[3].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/
         u_fifo_dc/*wp_sync2_r*[3].ff_inst}]
         ldc_create_group -name mc_rd_ctrl_rp_sync_b0 -bbox {1 1} [get_cells {*/lscc
         _lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_
         r*[0].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/
         u_fifo_dc/*rp_sync2_r*[0].ff_inst}]
         ldc_create_group -name mc_rd_ctrl_rp_sync_b1 -bbox {1 1} [get_cells {*/lscc
         _lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_
         r*[1].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/
         u_fifo_dc/*rp_sync2_r*[1].ff_inst}]
         ldc_create_group -name mc_rd_ctrl_rp_sync_b2 -bbox {1 1} [get_cells {*/lscc
         _lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_
         r*[2].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/ASYNC.u_ctrl_fifo/
         u_fifo_dc/*rp_sync2_r*[2].ff_inst}]
         ldc_create_group -name mc_wr_ctrl_rp_sync_b0 -bbox {1 1} [get_cells {*/lscc
         _lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_
         r*[0].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/
         u_fifo_dc/*rp_sync2_r*[0].ff_inst}]
         ldc_create_group -name mc_wr_ctrl_rp_sync_b1 -bbox {1 1} [get_cells {*/lscc
         _lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_
         r*[1].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/
         u_fifo_dc/*rp_sync2_r*[1].ff_inst}]
         ldc_create_group -name mc_wr_ctrl_rp_sync_b2 -bbox {1 1} [get_cells {*/lscc
         _lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/u_fifo_dc/*rp_sync1_
         r*[2].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_ctrl_fifo/
         u_fifo_dc/*rp_sync2_r*[2].ff_inst}]
         ldc_create_group -name mc_wr_data_rp_sync_b0 -bbox {1 1} [get_cells {*/lscc
         _lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync1_
         r*[0].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/
         u_fifo_dc/*rp_sync2_r*[0].ff_inst}]
         ldc_create_group -name mc_wr_data_rp_sync_b1 -bbox {1 1} [get_cells {*/lscc
         _lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync1_
         r*[1].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/
         u_fifo_dc/*rp_sync2_r*[1].ff_inst}]
         ldc_create_group -name mc_wr_data_rp_sync_b2 -bbox {1 1} [get_cells {*/lscc
         _lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync1_
         r*[2].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/
         u_fifo_dc/*rp_sync2_r*[2].ff_inst}]
         ldc_create_group -name mc_wr_data_rp_sync_b3 -bbox {1 1} [get_cells {*/lscc
         _lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/u_fifo_dc/*rp_sync1_
         r*[3].ff_inst */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/ASYNC.u_data_fifo/
         u_fifo_dc/*rp_sync2_r*[3].ff_inst}]
         set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/AS
         YNC.u_ctrl_fifo/u_fifo_dc/mem*.*_inst/WDO*] -datapath_only 4
         set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/AS
         YNC.u_ctrl_fifo/u_fifo_dc/mem*.*_inst/WDO*] -datapath_only 4
         set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_wr/AS
         YNC.u_data_fifo/u_fifo_dc/mem*.*_inst/WDO*] -datapath_only 4
         set_max_delay -from [get_pins */lscc_lpddr4_mc_inst/AXI_BI.u_axi_if/u_rd/u_
         reorder_buff/u_ctrl_dpram/lscc_distributed_dpram_inst/mem*.*_inst/WDO*]
         -datapath_only 4

    Run Time and Memory Usage

       Total CPU Time: 13 secs
       Total REAL Time: 14 secs
       Peak Memory Usage: 1222 MB
    Checksum -- map: 522bde57b3b5a42cd81faa75bacc134b7a1f95b
    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995
         AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent
         Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems
         All rights reserved.
    Copyright (c) 2002-2023 Lattice Semiconductor
         Corporation,  All rights reserved.