/*******************************************************************************
    Verilog netlist generated by IPGEN Lattice Radiant Software (64-bit)
    2023.2.0.38.1  Patch Version(s) 20248
    Soft IP Version: 2.1.0
    2024 03 18 12:29:22
*******************************************************************************/
/*******************************************************************************
    Wrapper Module generated per user settings.
*******************************************************************************/
module mem (pll_refclk_i, pll_rst_n_i, areset_n_i, aclk_i, rst_n_i, pclk_i,
    preset_n_i, pll_lock_o, sclk_o, irq_o, init_done_o, trn_err_o,
    axi_arvalid_i, axi_arid_i, axi_arlen_i, axi_arburst_i, axi_araddr_i,
    axi_arqos_i, axi_arsize_i, axi_arready_o, axi_rdata_o, axi_rresp_o,
    axi_rid_o, axi_rvalid_o, axi_rlast_o, axi_rready_i, axi_awvalid_i,
    axi_awid_i, axi_awlen_i, axi_awburst_i, axi_awaddr_i, axi_awqos_i,
    axi_awsize_i, axi_awready_o, axi_wvalid_i, axi_wdata_i, axi_wstrb_i,
    axi_wlast_i, axi_wready_o, axi_bvalid_o, axi_bready_i, axi_bresp_o,
    axi_bid_o, apb_penable_i, apb_psel_i, apb_pwrite_i, apb_paddr_i,
    apb_pwdata_i, apb_pready_o, apb_pslverr_o, apb_prdata_o, ddr_ck_o,
    ddr_cke_o, ddr_cs_o, ddr_ca_o, ddr_reset_n_o, ddr_dq_io, ddr_dqs_io,
    ddr_dmi_io)/* synthesis syn_black_box syn_declare_black_box=1 */;
    input  pll_refclk_i;
    input  pll_rst_n_i;
    input  areset_n_i;
    input  aclk_i;
    input  rst_n_i;
    input  pclk_i;
    input  preset_n_i;
    output  pll_lock_o;
    output  sclk_o;
    output  irq_o;
    output  init_done_o;
    output  trn_err_o;
    input  axi_arvalid_i;
    input  [3:0]  axi_arid_i;
    input  [7:0]  axi_arlen_i;
    input  [1:0]  axi_arburst_i;
    input  [29:0]  axi_araddr_i;
    input  [3:0]  axi_arqos_i;
    input  [2:0]  axi_arsize_i;
    output  axi_arready_o;
    output  [127:0]  axi_rdata_o;
    output  [1:0]  axi_rresp_o;
    output  [3:0]  axi_rid_o;
    output  axi_rvalid_o;
    output  axi_rlast_o;
    input  axi_rready_i;
    input  axi_awvalid_i;
    input  [3:0]  axi_awid_i;
    input  [7:0]  axi_awlen_i;
    input  [1:0]  axi_awburst_i;
    input  [29:0]  axi_awaddr_i;
    input  [3:0]  axi_awqos_i;
    input  [2:0]  axi_awsize_i;
    output  axi_awready_o;
    input  axi_wvalid_i;
    input  [127:0]  axi_wdata_i;
    input  [15:0]  axi_wstrb_i;
    input  axi_wlast_i;
    output  axi_wready_o;
    output  axi_bvalid_o;
    input  axi_bready_i;
    output  [1:0]  axi_bresp_o;
    output  [3:0]  axi_bid_o;
    input  apb_penable_i;
    input  apb_psel_i;
    input  apb_pwrite_i;
    input  [11:0]  apb_paddr_i;
    input  [31:0]  apb_pwdata_i;
    output  apb_pready_o;
    output  apb_pslverr_o;
    output  [31:0]  apb_prdata_o;
    output  [0:0]  ddr_ck_o;
    output  [0:0]  ddr_cke_o;
    output  [0:0]  ddr_cs_o;
    output  [5:0]  ddr_ca_o;
    output  ddr_reset_n_o;
    inout  [15:0]  ddr_dq_io;
    inout  [1:0]  ddr_dqs_io;
    inout  [1:0]  ddr_dmi_io;
endmodule