    BITGEN: Bitstream Generator Radiant Software (64-bit) 2023.2.0.38.1  Patch Version(s) 20248
    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.
    Mon Mar 18 12:45:32 2024

    Command: bitgen -w -gui -msgset /media/d480/GitHubProjects/TssTechnique/TssProjects/TssSemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/promote.xml -g REGISTER_INIT:ON lpddr4_axi_201_impl_1.udb /media/d480/GitHubProjects/TssTechnique/TssProjects/TssSemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/impl_1/lpddr4_axi_201_impl_1

    Running DRC.
    WARNING <71001209> - Disconnected tail of routing path on signal u_tragen.IMPL.sysmem0_inst.lscc_sys_mem_inst.bridge_s1.bridge_s1.n28 from driver R51C30_JF0_SLICED tail R51C30_JF0_SLICED.
    CRITICAL <71241010> - The clock port [LED[10]] is assigned to a non clock dedicated pin [R1], which might affect the clock performance. Use dedicated clock resources for the port.
    CRITICAL <71241010> - The clock port [LED[10]] is assigned to a non clock dedicated pin [R1], which might affect the clock performance. Use dedicated clock resources for the port.
    CRITICAL <71241010> - The clock port [LED[10]] is assigned to a non clock dedicated pin [R1], which might affect the clock performance. Use dedicated clock resources for the port.
    CRITICAL <71241010> - The clock port [LED[10]] is assigned to a non clock dedicated pin [R1], which might affect the clock performance. Use dedicated clock resources for the port.
    CRITICAL <71241010> - The clock port [LED[10]] is assigned to a non clock dedicated pin [R1], which might affect the clock performance. Use dedicated clock resources for the port.
    CRITICAL <71241010> - The clock port [LED[11]] is assigned to a non clock dedicated pin [R7], which might affect the clock performance. Use dedicated clock resources for the port.
    CRITICAL <71241010> - The clock port [LED[11]] is assigned to a non clock dedicated pin [R7], which might affect the clock performance. Use dedicated clock resources for the port.
    CRITICAL <71241010> - The clock port [LED[11]] is assigned to a non clock dedicated pin [R7], which might affect the clock performance. Use dedicated clock resources for the port.
    CRITICAL <71241010> - The clock port [LED[11]] is assigned to a non clock dedicated pin [R7], which might affect the clock performance. Use dedicated clock resources for the port.
    CRITICAL <71241010> - The clock port [LED[11]] is assigned to a non clock dedicated pin [R7], which might affect the clock performance. Use dedicated clock resources for the port.
    DRC detected 0 errors and 1 warnings.

    Preference Summary:

    +---------------------------------+---------------------------------+
    |  Preference                     |  Current Setting                |
    +---------------------------------+---------------------------------+
    |                        DONE_EX  |                           OFF*  |
    +---------------------------------+---------------------------------+
    |                        DONE_OD  |                            ON*  |
    +---------------------------------+---------------------------------+
    |                  CONFIG_SECURE  |                           OFF*  |
    +---------------------------------+---------------------------------+
    |               EARLY_IO_RELEASE  |                           OFF*  |
    +---------------------------------+---------------------------------+
    |                  REGISTER_INIT  |                           ON**  |
    +---------------------------------+---------------------------------+
    |   MASTER_PREAMBLE_TIMER_CYCLES  |                        600000*  |
    +---------------------------------+---------------------------------+
    |                 SLAVE_SPI_PORT  |                      DISABLE**  |
    +---------------------------------+---------------------------------+
    |                 SLAVE_I2C_PORT  |                      DISABLE**  |
    +---------------------------------+---------------------------------+
    |                 SLAVE_I3C_PORT  |                      DISABLE**  |
    +---------------------------------+---------------------------------+
    |                      JTAG_PORT  |                       ENABLE**  |
    +---------------------------------+---------------------------------+
    |                      DONE_PORT  |                       ENABLE**  |
    +---------------------------------+---------------------------------+
    |                     INITN_PORT  |                       ENABLE**  |
    +---------------------------------+---------------------------------+
    |                  PROGRAMN_PORT  |                       ENABLE**  |
    +---------------------------------+---------------------------------+
    |                        TRANSFR  |                           OFF*  |
    +---------------------------------+---------------------------------+
    |                MASTER_SPI_PORT  |                      DISABLE**  |
    +---------------------------------+---------------------------------+
    |                     MCCLK_FREQ  |                           3.5*  |
    +---------------------------------+---------------------------------+
    |                COMPRESS_CONFIG  |                           OFF*  |
    +---------------------------------+---------------------------------+
    |            BACKGROUND_RECONFIG  |                           OFF*  |
    +---------------------------------+---------------------------------+
    |                  CONFIG_IOSLEW  |                          SLOW*  |
    +---------------------------------+---------------------------------+
    |                        WAKE_UP  |              ENABLE_DONE_SYNC*  |
    +---------------------------------+---------------------------------+
    |                       BOOTMODE  |                          DUAL*  |
    +---------------------------------+---------------------------------+
    |         CONFIGIO_VOLTAGE_BANK0  |                 NOT_SPECIFIED*  |
    +---------------------------------+---------------------------------+
    |         CONFIGIO_VOLTAGE_BANK1  |                 NOT_SPECIFIED*  |
    +---------------------------------+---------------------------------+
     *  Default setting.
     ** The specified setting matches the default setting.

    Creating bit map...

    Bitstream Status: Final           Version 4.4.

    Saving bit stream in "/media/d480/GitHubProjects/TssTechnique/TssProjects/TssSemaDuinoQualif/td201_221014/lpddr4_axi/lpddr4_axi_201/impl_1/lpddr4_axi_201_impl_1.bit".
    Bitstream generation complete!