// Verilog netlist produced by program LSE 
// Netlist written on Mon Mar 18 12:31:19 2024
// Source file index table: 
// Object locations will have the form @<file_index>(<first_ line>[<left_column>],<last_line>[<right_column>])
// file 0 "/media/d480/Lattice/radiant/2023.2/ip/avant/fifo/rtl/lscc_fifo.v"
// file 1 "/media/d480/Lattice/radiant/2023.2/ip/avant/fifo_dc/rtl/lscc_fifo_dc.v"
// file 2 "/media/d480/Lattice/radiant/2023.2/ip/avant/ram_dp/rtl/lscc_ram_dp.v"
// file 3 "/media/d480/Lattice/radiant/2023.2/ip/avant/ram_dp_true/rtl/lscc_ram_dp_true.v"
// file 4 "/media/d480/Lattice/radiant/2023.2/ip/avant/ram_dq/rtl/lscc_ram_dq.v"
// file 5 "/media/d480/Lattice/radiant/2023.2/ip/avant/rom/rtl/lscc_rom.v"
// file 6 "/media/d480/Lattice/radiant/2023.2/ip/common/adder/rtl/lscc_adder.v"
// file 7 "/media/d480/Lattice/radiant/2023.2/ip/common/adder_subtractor/rtl/lscc_add_sub.v"
// file 8 "/media/d480/Lattice/radiant/2023.2/ip/common/complex_mult/rtl/lscc_complex_mult.v"
// file 9 "/media/d480/Lattice/radiant/2023.2/ip/common/counter/rtl/lscc_cntr.v"
// file 10 "/media/d480/Lattice/radiant/2023.2/ip/common/distributed_dpram/rtl/lscc_distributed_dpram.v"
// file 11 "/media/d480/Lattice/radiant/2023.2/ip/common/distributed_rom/rtl/lscc_distributed_rom.v"
// file 12 "/media/d480/Lattice/radiant/2023.2/ip/common/distributed_spram/rtl/lscc_distributed_spram.v"
// file 13 "/media/d480/Lattice/radiant/2023.2/ip/common/mult_accumulate/rtl/lscc_mult_accumulate.v"
// file 14 "/media/d480/Lattice/radiant/2023.2/ip/common/mult_add_sub/rtl/lscc_mult_add_sub.v"
// file 15 "/media/d480/Lattice/radiant/2023.2/ip/common/mult_add_sub_sum/rtl/lscc_mult_add_sub_sum.v"
// file 16 "/media/d480/Lattice/radiant/2023.2/ip/common/multiplier/rtl/lscc_multiplier.v"
// file 17 "/media/d480/Lattice/radiant/2023.2/ip/common/ram_shift_reg/rtl/lscc_shift_register.v"
// file 18 "/media/d480/Lattice/radiant/2023.2/ip/common/subtractor/rtl/lscc_subtractor.v"
// file 19 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_add.v"
// file 20 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_addsub.v"
// file 21 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_complex_mult.v"
// file 22 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_counter.v"
// file 23 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_distributed_dpram.v"
// file 24 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_distributed_rom.v"
// file 25 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_distributed_shift_reg.v"
// file 26 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_distributed_spram.v"
// file 27 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_fifo.v"
// file 28 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_fifo_dc.v"
// file 29 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_mac.v"
// file 30 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_mult.v"
// file 31 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_multaddsub.v"
// file 32 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_multaddsubsum.v"
// file 33 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_ram_dp.v"
// file 34 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_ram_dp_be.v"
// file 35 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_ram_dp_true.v"
// file 36 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_ram_dq.v"
// file 37 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_ram_dq_be.v"
// file 38 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_rom.v"
// file 39 "/media/d480/Lattice/radiant/2023.2/ip/pmi/pmi_sub.v"
// file 40 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/ACC54.v"
// file 41 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/ADC.v"
// file 42 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/ALUREG.v"
// file 43 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/BB_ADC.v"
// file 44 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/BB_CDR.v"
// file 45 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/BB_I3C_A.v"
// file 46 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/BFD1P3KX.v"
// file 47 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/BFD1P3LX.v"
// file 48 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/BNKREF18.v"
// file 49 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/CONFIG_IP.v"
// file 50 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/CONFIG_LMMIA.v"
// file 51 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/DDRDLL.v"
// file 52 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/DIFFCLKIO.v"
// file 53 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/DIFFIO18A.v"
// file 54 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/DLLDEL.v"
// file 55 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/DP16K.v"
// file 56 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/DPSC512K.v"
// file 57 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/DQSBUF.v"
// file 58 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/DQSBUFA.v"
// file 59 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/DQSBUF_IVREF.v"
// file 60 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/EBR.v"
// file 61 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/ECLKDIV.v"
// file 62 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/ECLKSYNC.v"
// file 63 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/FIFO16K.v"
// file 64 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/I2CFIFO.v"
// file 65 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/IFD1P3BX.v"
// file 66 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/IFD1P3DX.v"
// file 67 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/IFD1P3IX.v"
// file 68 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/IFD1P3JX.v"
// file 69 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/JTAG.v"
// file 70 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/LRAM.v"
// file 71 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/M18X36.v"
// file 72 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/MIPI.v"
// file 73 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/MULT18.v"
// file 74 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/MULT18X18.v"
// file 75 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/MULT18X36.v"
// file 76 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/MULT36.v"
// file 77 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/MULT36X36.v"
// file 78 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/MULT9.v"
// file 79 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/MULT9X9.v"
// file 80 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/MULTADDSUB18X18.v"
// file 81 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/MULTADDSUB18X18WIDE.v"
// file 82 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/MULTADDSUB18X36.v"
// file 83 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/MULTADDSUB36X36.v"
// file 84 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/MULTADDSUB9X9WIDE.v"
// file 85 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/MULTIBOOT.v"
// file 86 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/MULTPREADD18X18.v"
// file 87 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/MULTPREADD9X9.v"
// file 88 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/OFD1P3BX.v"
// file 89 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/OFD1P3DX.v"
// file 90 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/OFD1P3IX.v"
// file 91 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/OFD1P3JX.v"
// file 92 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/OSC.v"
// file 93 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/OSCA.v"
// file 94 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/PCIELL.v"
// file 95 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/PCSREFMUX.v"
// file 96 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/PCSX1.v"
// file 97 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/PCSX2.v"
// file 98 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/PCSX4.v"
// file 99 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/PDP16K.v"
// file 100 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/PDPSC16K.v"
// file 101 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/PDPSC512K.v"
// file 102 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/PLL.v"
// file 103 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/PLLA.v"
// file 104 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/PLLREFCS.v"
// file 105 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/PMU.v"
// file 106 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/PREADD9.v"
// file 107 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/REFMUX.v"
// file 108 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/REG18.v"
// file 109 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/SEDC.v"
// file 110 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/SEIO18A.v"
// file 111 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/SEIO33.v"
// file 112 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/SGMIICDR.v"
// file 113 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/SP16K.v"
// file 114 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/SP512K.v"
// file 115 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/TSALLA.v"
// file 116 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/lfcpnx/WDT.v"
// file 117 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/uaplatform/DPR16X4.v"
// file 118 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/uaplatform/FD1P3BX.v"
// file 119 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/uaplatform/FD1P3DX.v"
// file 120 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/uaplatform/FD1P3IX.v"
// file 121 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/uaplatform/FD1P3JX.v"
// file 122 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/uaplatform/GSR.v"
// file 123 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/uaplatform/IB.v"
// file 124 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/uaplatform/OB.v"
// file 125 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/uaplatform/OBZ.v"
// file 126 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/uaplatform/PCLKDIVSP.v"
// file 127 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/uaplatform/SPR16X4.v"
// file 128 "/media/d480/Lattice/radiant/2023.2/cae_library/simulation/verilog/uaplatform/WIDEFN9.v"

//
// Verilog Description of module mem
// module wrapper written out since it is a black-box. 
//

//

module mem (pll_refclk_i, pll_rst_n_i, areset_n_i, aclk_i, rst_n_i, 
            pclk_i, preset_n_i, pll_lock_o, sclk_o, irq_o, init_done_o, 
            trn_err_o, axi_arvalid_i, axi_arid_i, axi_arlen_i, axi_arburst_i, 
            axi_araddr_i, axi_arqos_i, axi_arsize_i, axi_arready_o, 
            axi_rdata_o, axi_rresp_o, axi_rid_o, axi_rvalid_o, axi_rlast_o, 
            axi_rready_i, axi_awvalid_i, axi_awid_i, axi_awlen_i, axi_awburst_i, 
            axi_awaddr_i, axi_awqos_i, axi_awsize_i, axi_awready_o, 
            axi_wvalid_i, axi_wdata_i, axi_wstrb_i, axi_wlast_i, axi_wready_o, 
            axi_bvalid_o, axi_bready_i, axi_bresp_o, axi_bid_o, apb_penable_i, 
            apb_psel_i, apb_pwrite_i, apb_paddr_i, apb_pwdata_i, apb_pready_o, 
            apb_pslverr_o, apb_prdata_o, ddr_ck_o, ddr_cke_o, ddr_cs_o, 
            ddr_ca_o, ddr_reset_n_o, ddr_dq_io, ddr_dqs_io, ddr_dmi_io) /* synthesis cpe_box=1 */ ;
    input pll_refclk_i;
    input pll_rst_n_i;
    input areset_n_i;
    input aclk_i;
    input rst_n_i;
    input pclk_i;
    input preset_n_i;
    output pll_lock_o;
    output sclk_o;
    output irq_o;
    output init_done_o;
    output trn_err_o;
    input axi_arvalid_i;
    input [3:0]axi_arid_i;
    input [7:0]axi_arlen_i;
    input [1:0]axi_arburst_i;
    input [29:0]axi_araddr_i;
    input [3:0]axi_arqos_i;
    input [2:0]axi_arsize_i;
    output axi_arready_o;
    output [127:0]axi_rdata_o;
    output [1:0]axi_rresp_o;
    output [3:0]axi_rid_o;
    output axi_rvalid_o;
    output axi_rlast_o;
    input axi_rready_i;
    input axi_awvalid_i;
    input [3:0]axi_awid_i;
    input [7:0]axi_awlen_i;
    input [1:0]axi_awburst_i;
    input [29:0]axi_awaddr_i;
    input [3:0]axi_awqos_i;
    input [2:0]axi_awsize_i;
    output axi_awready_o;
    input axi_wvalid_i;
    input [127:0]axi_wdata_i;
    input [15:0]axi_wstrb_i;
    input axi_wlast_i;
    output axi_wready_o;
    output axi_bvalid_o;
    input axi_bready_i;
    output [1:0]axi_bresp_o;
    output [3:0]axi_bid_o;
    input apb_penable_i;
    input apb_psel_i;
    input apb_pwrite_i;
    input [11:0]apb_paddr_i;
    input [31:0]apb_pwdata_i;
    output apb_pready_o;
    output apb_pslverr_o;
    output [31:0]apb_prdata_o;
    output [0:0]ddr_ck_o;
    output [0:0]ddr_cke_o;
    output [0:0]ddr_cs_o;
    output [5:0]ddr_ca_o;
    output ddr_reset_n_o;
    inout [15:0]ddr_dq_io;
    inout [1:0]ddr_dqs_io;
    inout [1:0]ddr_dmi_io;
    
    
    
endmodule
