    Copyright (c) 2002-2022 Lattice Semiconductor Corporation,  All rights reserved.

    Mon Mar 18 12:34:22 2024

    Command Line: par -w -n 1 -t 1 -s 1 -cores 1 -hsp m -exp parPathBased=ON \
    	lpddr4_axi_201_impl_1_map.udb lpddr4_axi_201_impl_1.udb

    Cost Table Summary
    Level/       Number       Estimated       Timing       Estimated Worst    Timing          Run      Run
    Cost [udb]   Unrouted     Worst Slack     Score        Slack(hold)        Score(hold)     Time     Status
    ----------   --------     -----------     ------       ---------------    -----------     ----     ------
    5_1   *      0            -3.007          601132       -                  -               09:53    Completed
    * : Design saved.

    Total (real) run time for 1-seed: 9 mins 55 secs

    par done!

    Lattice Place and Route Report for Design "lpddr4_axi_201_impl_1_map.udb"
    Mon Mar 18 12:34:22 2024

    Best Par Run
    PAR: Place And Route Radiant Software (64-bit) 2023.2.0.38.1  Patch Version(s) 20248.
    Command Line: par -w -t 1 -cores 1 -hsp m -exp parPathBased=ON \
    	lpddr4_axi_201_impl_1_map.udb lpddr4_axi_201_impl_1_par.dir/5_1.udb

    Loading lpddr4_axi_201_impl_1_map.udb ...
    Loading device for application GENERIC from file 'jd5d80.nph' in environment: /media/d480/Lattice/radiant/2023.2/ispfpga.
    Package Status:                     Final          Version 16.
    Performance Hardware Data Status:   Final          Version 3.9.

    Design:  eval_top
    Family:  LFCPNX
    Device:  LFCPNX-100
    Package: BBG484
    Performance Grade:   9_High-Performance_1.0V

    Device SLICE utilization summary after final SLICE packing:
       SLICE          20061/39936        50% used

    Number of Signals: 31106
    Number of Connections: 104498

    Device utilization summary:

       VHI                   1/1           100% used
       EBR                  41/208          20% used
       DIFFIO18A             4/66            6% used
                             4/66            6% bonded
       DDRDLL                1/2            50% used
       DQSBUFA               2/11           18% used
       IOLOGIC              29/132          22% used
       SEIO18A              35/132          27% used
                            35/132          26% bonded
       SEIO33               27/299           9% used
                            27/167          16% bonded
       ECLKDIV               1/12            8% used
       ECLKSYNC              1/12            8% used
       OSC                   1/1           100% used
       PLL                   2/4            50% used
       IVREF                 2/11           18% used
       SLICE             20061/39936        50% used
         LUT             18915/79872        24% used
         REG             10708/79872        13% used

    Pin Constraint Summary:
       42 out of 58 pins locked (72% locked).
    .
    .

    .
    Starting Placer Phase 0 (HIER). CPU time: 24 secs , REAL time: 24 secs
    ............
    Finished Placer Phase 0 (HIER). CPU time: 38 secs , REAL time: 38 secs

    Starting Placer Phase 1. CPU time: 39 secs , REAL time: 39 secs
    ..  ..
    .................

    Placer score = 12678021.
    Finished Placer Phase 1. CPU time: 8 mins 12 secs , REAL time: 8 mins 12 secs

    Starting Placer Phase 2.
    .

    Placer score =  11946141
    Finished Placer Phase 2.  CPU time: 8 mins 28 secs , REAL time: 8 mins 29 secs

    After final PLC packing legalization, all 0 SLICEs that were not satisfying 1 CLK/CE/LSR per HALF-PLC restriction are all placed into compatible PLCs.

    Clock Report

    Global Clock Resources:
      CLK_PIN    : 0 out of 26 (0%)
      PLL        : 2 out of 4 (50%)
      PCS        : 0 out of 2 (0%)
      DCS        : 0 out of 2 (0%)
      DCC        : 0 out of 62 (0%)
      ECLKDIV    : 1 out of 12 (8%)
      PCLKDIV    : 0 out of 2 (0%)
      OSC        : 1 out of 1 (100%)

    Global Clocks:
      PRIMARY "sclk_o" from comp "u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u1_clock_sync.u0_ECLKDIV.ECLKDIV_inst" on ECLKDIV_CORE site "ECLKDIV_CORE_R73C74B", clk load = 6014, ce load = 0, sr load = 0
      PRIMARY "osc_clk_90" from HFCLKOUT on comp "osc_int_inst.lscc_osc_inst.u_OSC.OSCA_inst" on site "OSC_CORE_R1C137", clk load = 1, ce load = 0, sr load = 0
      PRIMARY "out_clk1_c" from CLKOS on comp "ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst" on PLL site "PLL_ULC", clk load = 2770, ce load = 0, sr load = 0
      PRIMARY "clk_w" from CLKOP on comp "ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst" on PLL site "PLL_ULC", clk load = 1922, ce load = 0, sr load = 0
      PRIMARY "u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.fbclk_w" from CLKOP on comp "u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst" on PLL site "PLL_LLC", clk load = 1, ce load = 0, sr load = 0
      PRIMARY "u_mem.lscc_lpddr4_mc_inst.srst_n" from Q0 on comp "u_mem.lscc_lpddr4_mc_inst.srst_n_c.SLICE_12562" on site "R38C74A", clk load = 0, ce load = 1, sr load = 4199
      PRIMARY "areset_n_i" from Q0 on comp "areset_n.SLICE_12779" on site "R38C74C", clk load = 0, ce load = 2, sr load = 1093
      PRIMARY "u_tragen.cpu0_inst_system_resetn_o_net" from Q0 on comp "u_tragen.cpu0_inst.reset_n_o.SLICE_3872" on site "R38C73A", clk load = 0, ce load = 0, sr load = 1042
      PRIMARY "u_mem.lscc_lpddr4_mc_inst.phy_srst_n" from Q0 on comp "u_mem.lscc_lpddr4_mc_inst.phy_srst_n_c.SLICE_12566" on site "R38C73C", clk load = 0, ce load = 1, sr load = 930
      PRIMARY "u_mem.lscc_lpddr4_mc_inst.arst_n" from Q0 on comp "u_mem.lscc_lpddr4_mc_inst.arst_n_c.SLICE_12564" on site "R72C71A", clk load = 0, ce load = 0, sr load = 733
      PRIMARY "preset_n_i" from Q0 on comp "prst_n.SLICE_12787" on site "R72C72A", clk load = 0, ce load = 0, sr load = 305

      PRIMARY  : 11 out of 16 (68%)

    Edge Clocks:

      ECLK "u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w": BANK3_ECLK1
        - From GPLL_CLKOS "PLL_LLC".CLKOS, driver "u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst".
      ECLK "u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w": BANK4_ECLK1
        - From GPLL_CLKOS "PLL_LLC".CLKOS, driver "u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst".

    I/O Usage Summary (final):
       27 out of 299 (9.0%) SEIO33 sites used.
       27 out of 167 (16.2%) bonded SEIO33 sites used.
       Number of SEIO33 components: 27; differential: 0
       Number of Vref pins used: 0
       31 out of 132 (23.5%) SEIO18 sites used.
       31 out of 132 (23.5%) bonded SEIO18 sites used.
       Number of SEIO18 components: 31; differential: 4
       4 out of 66 (6.1%) DIFFIO18 sites used.
       4 out of 66 (6.1%) bonded DIFFIO18 sites used.
       Number of DIFFIO18 components: 4; differential: 4

    I/O Bank Usage Summary:
    +----------+----------------+------------+------------+------------+
    | I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
    +----------+----------------+------------+------------+------------+
    | 0        | 3 / 24 ( 12%)  | 3.3V       | -          | -          |
    | 1        | 4 / 39 ( 10%)  | 3.3V       | -          | -          |
    | 2        | 4 / 32 ( 12%)  | 3.3V       | -          | -          |
    | 3        | 16 / 48 ( 33%) | 1.1V       | -          | -          |
    | 4        | 17 / 48 ( 35%) | 1.1V       | -          | -          |
    | 5        | 2 / 36 (  5%)  | 1.1V       | -          | -          |
    | 6        | 5 / 32 ( 15%)  | 3.3V       | -          | -          |
    | 7        | 11 / 40 ( 27%) | 3.3V       | -          | -          |
    +----------+----------------+------------+------------+------------+

    Total Placer CPU time: 8 mins 29 secs , REAL time: 8 mins 29 secs

    Checksum -- place: 6e95b9ce53208253a596dc7f7dac9aba4de6cf
    Writing design to file lpddr4_axi_201_impl_1_par.dir/5_1.udb ...

    CRITICAL <71241010> - par: The clock port [LED[10]] is assigned to a non clock dedicated pin [R1], which might affect the clock performance. Use dedicated clock resources for the port.
    CRITICAL <71241010> - par: The clock port [LED[10]] is assigned to a non clock dedicated pin [R1], which might affect the clock performance. Use dedicated clock resources for the port.
    CRITICAL <71241010> - par: The clock port [LED[10]] is assigned to a non clock dedicated pin [R1], which might affect the clock performance. Use dedicated clock resources for the port.
    CRITICAL <71241010> - par: The clock port [LED[10]] is assigned to a non clock dedicated pin [R1], which might affect the clock performance. Use dedicated clock resources for the port.
    CRITICAL <71241010> - par: The clock port [LED[10]] is assigned to a non clock dedicated pin [R1], which might affect the clock performance. Use dedicated clock resources for the port.
    CRITICAL <71241010> - par: The clock port [LED[11]] is assigned to a non clock dedicated pin [R7], which might affect the clock performance. Use dedicated clock resources for the port.
    CRITICAL <71241010> - par: The clock port [LED[11]] is assigned to a non clock dedicated pin [R7], which might affect the clock performance. Use dedicated clock resources for the port.
    CRITICAL <71241010> - par: The clock port [LED[11]] is assigned to a non clock dedicated pin [R7], which might affect the clock performance. Use dedicated clock resources for the port.
    CRITICAL <71241010> - par: The clock port [LED[11]] is assigned to a non clock dedicated pin [R7], which might affect the clock performance. Use dedicated clock resources for the port.
    CRITICAL <71241010> - par: The clock port [LED[11]] is assigned to a non clock dedicated pin [R7], which might affect the clock performance. Use dedicated clock resources for the port.

    Start NBR router at Mon Mar 18 12:42:56 CET 2024

    *****************************************************************
    Info: NBR allows conflicts(one node used by more than one signal)
          in the earlier iterations. In each iteration, it tries to
          solve the conflicts while keeping the critical connections
          routed as short as possible. The routing process is said to
          be completed when no conflicts exist and all connections
          are routed.
    Note: NBR uses a different method to calculate timing slacks. The
          worst slack and total negative slack may not be the same as
          that in timing report. You should always run the timing
          tool to verify your design.
    *****************************************************************

    Starting routing resource preassignment
    WARNING <62243001> - par: The external feedback signal u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.fbclk_w for PLL_CORE instance u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst drives neither primary nor edge clock loads. Please review this PLL feedback connection in your design.
    INFO <62244000> - par: The external feedback signal u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.fbclk_w for PLL_CORE instance u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.gen_no_refclk_mon.u_PLL.PLL_inst will use the primary clock network.
    INFO <62244000> - par: The external feedback signal clk_w for PLL_CORE instance ASYNC_AXI.u_aclk_pclk.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst will use the primary clock network.
    Preassignment Summary:
    --------------------------------------------------------------------------------
    10705 connections routed with dedicated routing resources
    11 global clock signals routed
    29940 connections routed (of 104498 total) (28.65%)
    ---------------------------------------------------------
    Clock routing summary:
    Primary clocks (44 used out of 64 available):
        Signal "out_clk1_c" (4, 20, 36, 52)
           Clock   loads: 2770  out of  2770 routed (100.00%)
           Data    loads: 0     out of     1 routed (  0.00%)
        Signal "u_tragen.cpu0_inst_system_resetn_o_net" (5, 21, 37, 53)
           Control loads: 1042  out of  1042 routed (100.00%)
           Data    loads: 0     out of     8 routed (  0.00%)
        Signal "clk_w" (3, 19, 35, 51)
           Clock   loads: 1922  out of  1922 routed (100.00%)
        Signal "sclk_o" (1, 17, 33, 49)
           Clock   loads: 6014  out of  6014 routed (100.00%)
        Signal "areset_n_i" (10, 26, 42, 58)
           Control loads: 1095  out of  1095 routed (100.00%)
           Data    loads: 0     out of     1 routed (  0.00%)
        Signal "osc_clk_90" (7, 23, 39, 55)
           Clock   loads: 1     out of     1 routed (100.00%)
        Signal "u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_pll.fbclk_w" (2, 18, 34, 50)
           Clock   loads: 1     out of     1 routed (100.00%)
        Signal "u_mem.lscc_lpddr4_mc_inst.phy_srst_n" (9, 25, 41, 57)
           Control loads: 931   out of   931 routed (100.00%)
           Data    loads: 0     out of     2 routed (  0.00%)
        Signal "preset_n_i" (11, 27, 43, 59)
           Control loads: 305   out of   305 routed (100.00%)
        Signal "u_mem.lscc_lpddr4_mc_inst.srst_n" (0, 16, 32, 48)
           Control loads: 4200  out of  4200 routed (100.00%)
           Data    loads: 0     out of    29 routed (  0.00%)
        Signal "u_mem.lscc_lpddr4_mc_inst.arst_n" (8, 24, 40, 56)
           Control loads: 733   out of   733 routed (100.00%)
    Other clocks:
        Signal "axi_wstrb_i[0]"
           Clock   loads: 3     out of     3 routed (100.00%)
           Control loads: 21    out of    21 routed (100.00%)
           Data    loads: 197   out of   197 routed (100.00%)
        Signal "pll_refclk_i_c"
           Clock   loads: 1     out of     1 routed (100.00%)
        Signal "u_mem.lscc_lpddr4_mc_inst.u_lp4mem.eclkout_w"
           Clock   loads: 33    out of    33 routed (100.00%)
        Signal "u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw_w[0]"
           Clock   loads: 1     out of     1 routed (100.00%)
        Signal "u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw270_w[1]"
           Clock   loads: 9     out of     9 routed (100.00%)
        Signal "u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw_w[1]"
           Clock   loads: 1     out of     1 routed (100.00%)
        Signal "u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsw270_w[0]"
           Clock   loads: 9     out of     9 routed (100.00%)
        Signal "u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsr90_w[0]"
           Clock   loads: 8     out of     8 routed (100.00%)
        Signal "u_mem.lscc_lpddr4_mc_inst.u_lp4mem.u_dq_dqs_dm.dqsr90_w[1]"
           Clock   loads: 8     out of     8 routed (100.00%)
    ---------------------------------------------------------
    --------------------------------------------------------------------------------
    Completed routing resource preassignment
    +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    Routing in Serial Mode ......
    +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Start NBR section for initial routing at Mon Mar 18 12:43:13 CET 2024
    Level 4, iteration 1
    15945(0.37%) conflicts; 0(0.00%) untouched conn; 1199510 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -3.007ns/-1199.511ns; real time: 37 secs

    Info: Initial congestion level at 75.00% usage is 0
    Info: Initial congestion area  at 75.00% usage is 0 (0.00%)

    Start NBR section for normal routing at Mon Mar 18 12:43:32 CET 2024
    Level 4, iteration 1
    12499(0.29%) conflicts; 0(0.00%) untouched conn; 1201762 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -3.007ns/-1201.763ns; real time: 46 secs
    Level 4, iteration 2
    3756(0.09%) conflicts; 0(0.00%) untouched conn; 1201762 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -3.007ns/-1201.763ns; real time: 53 secs
    Level 4, iteration 3
    1843(0.04%) conflicts; 0(0.00%) untouched conn; 1201710 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -3.007ns/-1201.711ns; real time: 58 secs
    Level 4, iteration 4
    758(0.02%) conflicts; 0(0.00%) untouched conn; 1201710 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -3.007ns/-1201.711ns; real time: 1 mins 1 secs
    Level 4, iteration 5
    413(0.01%) conflicts; 0(0.00%) untouched conn; 1204125 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -3.007ns/-1204.126ns; real time: 1 mins 3 secs
    Level 4, iteration 6
    228(0.01%) conflicts; 0(0.00%) untouched conn; 1204125 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -3.007ns/-1204.126ns; real time: 1 mins 4 secs
    Level 4, iteration 7
    119(0.00%) conflicts; 0(0.00%) untouched conn; 1204125 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -3.007ns/-1204.126ns; real time: 1 mins 6 secs
    Level 4, iteration 8
    52(0.00%) conflicts; 0(0.00%) untouched conn; 1204125 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -3.007ns/-1204.126ns; real time: 1 mins 6 secs
    Level 4, iteration 9
    19(0.00%) conflicts; 0(0.00%) untouched conn; 1204125 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -3.007ns/-1204.126ns; real time: 1 mins 8 secs
    Level 4, iteration 10
    5(0.00%) conflicts; 0(0.00%) untouched conn; 1204125 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -3.007ns/-1204.126ns; real time: 1 mins 8 secs
    Level 4, iteration 11
    3(0.00%) conflicts; 0(0.00%) untouched conn; 1204125 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -3.007ns/-1204.126ns; real time: 1 mins 9 secs
    Level 4, iteration 12
    1(0.00%) conflict; 0(0.00%) untouched conn; 1204125 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -3.007ns/-1204.126ns; real time: 1 mins 10 secs
    Level 4, iteration 13
    0(0.00%) conflict; 0(0.00%) untouched conn; 1204125 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -3.007ns/-1204.126ns; real time: 1 mins 11 secs

    Start NBR section for post-routing at Mon Mar 18 12:44:06 CET 2024

    End NBR router with 0 unrouted connection

    Checksum -- route: 28f1539d3c8e687b544864b2aa631c61595d3030

    Total CPU time 1 mins 16 secs
    Total REAL time: 1 mins 16 secs
    Completely routed.
    End of route.  104498 routed (100.00%); 0 unrouted.

    Writing design to file lpddr4_axi_201_impl_1_par.dir/5_1.udb ...

    All signals are completely routed.

    PAR_SUMMARY::Run status = Completed
    PAR_SUMMARY::Number of unrouted conns = 0
    PAR_SUMMARY::Estimated worst slack<setup/<ns>> = -3.007
    PAR_SUMMARY::Timing score<setup/<ns>> = 601.133
    PAR_SUMMARY::Estimated worst slack<hold/<ns>> = <n/a>
    PAR_SUMMARY::Timing score<hold/<ns>> = <n/a>
    PAR_SUMMARY::Number of errors = 0

    Note: user must run 'timing' for timing closure signoff.

    Total CPU  Time: 9 mins 55 secs
    Total REAL Time: 9 mins 55 secs
    Peak Memory Usage: 1607.23 MB

    par done!

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.